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AD7888ARZ-REEL7

Analog Devices · Analog To Digital Converters (ADCs) · SOIC-16

AD7888ARZ-REEL7 from Analog Devices, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS input Chip Select, active-low logic input that initiates conversions and frames the serial data transfer.
2 REF IN/REF OUT bidirectional On-chip 2.5 V reference is available on this pin, or an external reference from 1.2 V to VDD can be applied to it after the internal reference is disabled.
3 VDD power_in Power supply input with a range of 2.7 V to 5.25 V.
4 AGND power_in Analog ground reference point for all circuitry; all analog input and external reference signals are referred to this pin, and it should connect to the system AGND plane.
5 AIN1 input Single-ended analog input channel 1 multiplexed into the track/hold, with input range 0 to VREF; unused channels should be connected to AGND.
6 AIN2 input Single-ended analog input channel 2 multiplexed into the track/hold, with input range 0 to VREF; unused channels should be connected to AGND.
7 AIN3 input Single-ended analog input channel 3 multiplexed into the track/hold, with input range 0 to VREF; unused channels should be connected to AGND.
8 AIN4 input Single-ended analog input channel 4 multiplexed into the track/hold, with input range 0 to VREF; unused channels should be connected to AGND.
9 AIN5 input Single-ended analog input channel 5 multiplexed into the track/hold, with input range 0 to VREF; unused channels should be connected to AGND.
10 AIN6 input Single-ended analog input channel 6 multiplexed into the track/hold, with input range 0 to VREF; unused channels should be connected to AGND.
11 AIN7 input Single-ended analog input channel 7 multiplexed into the track/hold, with input range 0 to VREF; unused channels should be connected to AGND.
12 AIN8 input Single-ended analog input channel 8 multiplexed into the track/hold, with input range 0 to VREF; unused channels should be connected to AGND.
13 AGND power_in Analog ground reference point for all circuitry; both AGND pins should connect to the system AGND plane.
14 DIN input Data In logic input; data written to the Control Register is clocked in on the rising edge of SCLK.
15 DOUT output Data Out logic output providing the serial conversion result (four leading zeros then 12 bits, MSB first), clocked out on the falling edge of SCLK.
16 SCLK input Serial clock logic input for data access and control register writes, also the clock source for the conversion process; maximum fSCLK is 2 MHz.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-16
Category ADC/DAC/Data Conversion
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Integral Nonlinearity (A Version) -2 2 LSB 2
Differential Nonlinearity (A Version) -2 2 LSB Guaranteed No Missed Codes to 11 Bits (A Grade) 2
Offset Error -6 6 LSB VDD = 4.75 V to 5.25 V 2
Offset Error -4.5 4.5 LSB VDD = 2.7 V to 3.6 V 2
Gain Error -2 2 LSB 2
Gain Error Match 3 LSB 2
Leakage Current -1 1 µA 2
REFIN Input Voltage Range 2.5 V Functional from 1.2 V 2
REFOUT Output Voltage 2.45 2.55 V 2
Input High Voltage VINH 2.4 V VDD = 4.75 V to 5.25 V 2
Input High Voltage VINH 2.1 V VDD = 2.7 V to 3.6 V 2
Input Low Voltage VINL 0.8 V VDD = 2.7 V to 5.25 V 2
Input Current IIN -10 10 µA Typically 10 nA, VIN = 0 V or VDD 2
Input Capacitance CIN 10 pF 2
Output Low Voltage VOL 0.4 V ISINK = 200 µA 2
Floating-State Leakage Current -10 10 µA 2
Floating-State Output Capacitance 10 pF 2
VDD Supply Range VDD 2.7 5.25 V 3
IDD Normal Mode (Static) IDD 700 µA 3
Shutdown Mode IDD IDD 22 µA VDD = 4.75 V to 5.25 V 3
Shutdown Mode IDD IDD 11 µA VDD = 2.7 V to 3.6 V 3
Normal-Mode Power Dissipation 3.5 mW VDD = 5 V 3
Normal-Mode Power Dissipation 2.1 mW VDD = 3 V 3
Shutdown Power Dissipation 10 µW VDD = 5 V 3
Shutdown Power Dissipation 33 µW VDD = 3 V 3
Standby Power Dissipation 1 mW VDD = 5 V 3
Standby Power Dissipation 600 µW VDD = 3 V 3
VDD to AGND VDD -0.3 7 V 3
Analog Input Voltage to AGND -0.3 V Maximum VDD + 0.3 V 3
Digital Input Voltage to AGND -0.3 V Maximum VDD + 0.3 V 3
Digital Output Voltage to AGND -0.3 V Maximum VDD + 0.3 V 3
REFIN/REFOUT to AGND -0.3 V Maximum VDD + 0.3 V 3
Input Current to Any Pin Except Supplies -10 10 mA Transient, see note 2 3
Operating Temperature Range (A Version) -40 105 °C 3
Storage Temperature Range -65 150 °C 3
Junction Temperature 150 °C 3
SOIC, TSSOP Package Power Dissipation 450 mW 3
Max Clock Frequency fSCLK 2 MHz VDD = 4.75 V to 5.25 V 4
CS to SCLK Setup Time t1 10 ns 4
Delay from CS until DOUT 3-State Disabled t2 30 ns VDD = 4.75 V to 5.25 V 4
Delay from CS until DOUT 3-State Disabled t2 60 ns VDD = 2.7 V to 3.6 V 4
Data Access Time after SCLK Falling Edge t3 75 ns VDD = 4.75 V to 5.25 V 4
Data Access Time after SCLK Falling Edge t3 100 ns VDD = 2.7 V to 3.6 V 4
Data Setup Time Prior to SCLK Rising Edge t4 20 ns 4
Data Valid to SCLK Hold Time t5 20 ns 4
SCLK High Pulsewidth t6 0.4 tSCLK 4
SCLK Low Pulsewidth t7 0.4 tSCLK 4
CS Rising Edge to DOUT High Impedance t8 80 ns VDD = 4.75 V to 5.25 V 4
Junction-to-Ambient Thermal Impedance (SOIC) θJA 124.9 °C/W 3
Junction-to-Case Thermal Impedance (SOIC) θJC 42.9 °C/W 3
Offset Error Match 2 LSB 2
Input Capacitance (Track) 38 pF When in Track 2
Input Capacitance (Hold) 4 pF When in Hold 2
Input Impedance 5 kΩ Very High Impedance If Internal Reference Disabled 2
IDD Normal Mode (Operational) IDD 700 µA fSAMPLE = 125 kSPS 3
IDD Using Standby Mode IDD 450 µA fSAMPLE = 50 kSPS 3
REFOUT Tempco 50 ppm/°C 2
Power-Up Time from Shutdown t9 55 µs 4

CAD (KiCad official)

  • Symbol: AD7888ARZ-REEL7
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: ad7888arz-reel7-etched.step / ad7888arz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7888arz-reel7.step / ad7888arz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (17 pp, sha256 e9e996fd3d3320fd, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF