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AD7866BRUZ
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADCs), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD7866BRUZ
Analog Devices · Analog To Digital Converters (ADCs) · TSSOP-20
AD7866BRUZ from Analog Devices, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | REF SELECT | input | Logic input that selects the on-chip 2.5 V reference when tied to GND, or an external reference through VREF when tied to logic high. |
| 2 | DCAPB | passive | Decoupling capacitor connection for the ADC B reference buffer, which can also take the on-chip reference out or input a separate external reference. |
| 3 | AGND | power_in | Analog ground reference for all analog circuitry, which must not be more than 0.3 V from DGND even on a transient basis. |
| 4 | VB2 | input | Single-ended analog input channel 2 of ADC B, with an input range of 0 V to VREF or 2 x VREF set by RANGE at the falling edge of CS. |
| 5 | VB1 | input | Single-ended analog input channel 1 of ADC B, with an input range of 0 V to VREF or 2 x VREF set by RANGE at the falling edge of CS. |
| 6 | VA2 | input | Single-ended analog input channel 2 of ADC A, with an input range of 0 V to VREF or 2 x VREF set by RANGE at the falling edge of CS. |
| 7 | VA1 | input | Single-ended analog input channel 1 of ADC A, with an input range of 0 V to VREF or 2 x VREF set by RANGE at the falling edge of CS. |
| 8 | AGND | power_in | Analog ground reference for all analog circuitry, which must not be more than 0.3 V from DGND even on a transient basis. |
| 9 | DCAPA | passive | Decoupling capacitor connection for the ADC A reference buffer, which can also take the on-chip reference out or input a separate external reference. |
| 10 | VREF | power_in | Reference decoupling pin connected to the internal 2.5 V reference, which requires a decoupling capacitor and serves as the external reference input when REF SELECT is high. |
| 11 | RANGE | input | Logic input sampled on the falling edge of CS that sets the input range (low for 0 V to VREF with straight binary, high for 2 x VREF with twos complement). |
| 12 | AVDD | power_in | Analog supply voltage of 2.7 V to 5.25 V that must stay within 0.3 V of DVDD even on a transient basis. |
| 13 | DVDD | power_in | Digital supply voltage of 2.7 V to 5.25 V that must stay within 0.3 V of AVDD even on a transient basis. |
| 14 | DGND | power_in | Digital ground reference for all digital circuitry, which must not be more than 0.3 V from AGND even on a transient basis. |
| 15 | DOUTA | output | Serial data output for ADC A that clocks out on the falling edge of SCLK, MSB first, after one leading zero and three STATUS bits. |
| 16 | DOUTB | output | Serial data output for ADC B that clocks out on the falling edge of SCLK, MSB first, after one leading zero and three STATUS bits. |
| 17 | VDRIVE | power_in | Logic power supply input that sets the voltage level at which the digital interface operates and should be decoupled to DGND. |
| 18 | SCLK | input | Serial clock logic input that clocks out the conversion data and sets the conversion rate. |
| 19 | CS | input | Active-low chip select logic input that initiates conversions on its falling edge and frames the serial data transfer. |
| 20 | A0 | input | Multiplexer select logic input, sampled on the falling edge of CS, that chooses Channel 1 (low) or Channel 2 (high) of both ADCs for the next conversion. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-20 |
| Category | Data Converters |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
AD7866BRUZ - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
ad7866bruz-etched.step/ad7866bruz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7866bruz.step/ad7866bruz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (24 pp, sha256
97330acd060d2794, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD7866BRUZ
**Analog Devices** · Analog To Digital Converters (ADCs) · TSSOP-20
AD7866BRUZ from Analog Devices, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | REF SELECT | input | Logic input that selects the on-chip 2.5 V reference when tied to GND, or an external reference through VREF when tied to logic high. |
| 2 | DCAPB | passive | Decoupling capacitor connection for the ADC B reference buffer, which can also take the on-chip reference out or input a separate external reference. |
| 3 | AGND | power_in | Analog ground reference for all analog circuitry, which must not be more than 0.3 V from DGND even on a transient basis. |
| 4 | VB2 | input | Single-ended analog input channel 2 of ADC B, with an input range of 0 V to VREF or 2 x VREF set by RANGE at the falling edge of CS. |
| 5 | VB1 | input | Single-ended analog input channel 1 of ADC B, with an input range of 0 V to VREF or 2 x VREF set by RANGE at the falling edge of CS. |
| 6 | VA2 | input | Single-ended analog input channel 2 of ADC A, with an input range of 0 V to VREF or 2 x VREF set by RANGE at the falling edge of CS. |
| 7 | VA1 | input | Single-ended analog input channel 1 of ADC A, with an input range of 0 V to VREF or 2 x VREF set by RANGE at the falling edge of CS. |
| 8 | AGND | power_in | Analog ground reference for all analog circuitry, which must not be more than 0.3 V from DGND even on a transient basis. |
| 9 | DCAPA | passive | Decoupling capacitor connection for the ADC A reference buffer, which can also take the on-chip reference out or input a separate external reference. |
| 10 | VREF | power_in | Reference decoupling pin connected to the internal 2.5 V reference, which requires a decoupling capacitor and serves as the external reference input when REF SELECT is high. |
| 11 | RANGE | input | Logic input sampled on the falling edge of CS that sets the input range (low for 0 V to VREF with straight binary, high for 2 x VREF with twos complement). |
| 12 | AVDD | power_in | Analog supply voltage of 2.7 V to 5.25 V that must stay within 0.3 V of DVDD even on a transient basis. |
| 13 | DVDD | power_in | Digital supply voltage of 2.7 V to 5.25 V that must stay within 0.3 V of AVDD even on a transient basis. |
| 14 | DGND | power_in | Digital ground reference for all digital circuitry, which must not be more than 0.3 V from AGND even on a transient basis. |
| 15 | DOUTA | output | Serial data output for ADC A that clocks out on the falling edge of SCLK, MSB first, after one leading zero and three STATUS bits. |
| 16 | DOUTB | output | Serial data output for ADC B that clocks out on the falling edge of SCLK, MSB first, after one leading zero and three STATUS bits. |
| 17 | VDRIVE | power_in | Logic power supply input that sets the voltage level at which the digital interface operates and should be decoupled to DGND. |
| 18 | SCLK | input | Serial clock logic input that clocks out the conversion data and sets the conversion rate. |
| 19 | CS | input | Active-low chip select logic input that initiates conversions on its falling edge and frames the serial data transfer. |
| 20 | A0 | input | Multiplexer select logic input, sampled on the falling edge of CS, that chooses Channel 1 (low) or Channel 2 (high) of both ADCs for the next conversion. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-20 |
| Category | Data Converters |
| Pins | 20 |
## CAD (KiCad official)
- Symbol: `AD7866BRUZ`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `ad7866bruz-etched.step` / `ad7866bruz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7866bruz.step` / `ad7866bruz.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7866.pdf) (24 pp, sha256 `97330acd060d2794`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad7866bruz-datasheet.pdf)