AD7866ARUZ from Analog Devices, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	REF SELECT	input	Logic input selecting internal or external reference: tied to GND uses the on-chip 2.5 V reference for both ADCs, tied high allows an external reference through VREF.
2	DCAPB	passive	Decoupling capacitor connection for the ADC B reference buffer; the on-chip reference can be taken from it or a separate external reference applied depending on REF SELECT and VREF configuration.
3	AGND	power_in	Analog ground reference for all analog circuitry, to be connected to the system AGND plane and kept within 0.3 V of DGND.
4	VB2	input	Single-ended analog input channel 2 of ADC B, with 0 V to VREF or 2 x VREF range depending on the RANGE pin at the falling edge of CS.
5	VB1	input	Single-ended analog input channel 1 of ADC B, with 0 V to VREF or 2 x VREF range depending on the RANGE pin at the falling edge of CS.
6	VA2	input	Single-ended analog input channel 2 of ADC A, with 0 V to VREF or 2 x VREF range depending on the RANGE pin at the falling edge of CS.
7	VA1	input	Single-ended analog input channel 1 of ADC A, with 0 V to VREF or 2 x VREF range depending on the RANGE pin at the falling edge of CS.
8	AGND	power_in	Analog ground reference for all analog circuitry, to be connected to the system AGND plane and kept within 0.3 V of DGND.
9	DCAPA	passive	Decoupling capacitor connection for the ADC A reference buffer; the on-chip reference can be taken from it or a separate external reference applied depending on REF SELECT and VREF configuration.
10	VREF	power_in	Reference decoupling and external reference selection pin, connected to the internal 2.5 V nominal reference and requiring a decoupling capacitor.
11	RANGE	input	Logic input selecting analog input range and output coding, checked at the falling edge of CS: low gives 0 V to VREF with straight binary, high gives 2 x VREF with twos complement.
12	AVDD	power_in	Analog supply voltage, 2.7 V to 5.25 V, within 0.3 V of DVDD and decoupled to AGND.
13	DVDD	power_in	Digital supply voltage, 2.7 V to 5.25 V, within 0.3 V of AVDD and decoupled to DGND.
14	DGND	power_in	Digital ground reference for all digital circuitry, within 0.3 V of AGND.
15	DOUTA	output	Serial data output for ADC A, clocked out MSB first on the falling edge of SCLK with one leading zero, three status bits and 12 data bits.
16	DOUTB	output	Serial data output for ADC B, clocked out MSB first on the falling edge of SCLK with one leading zero, three status bits and 12 data bits.
17	VDRIVE	power_in	Logic power supply input that sets the interface operating voltage, to be decoupled to DGND.
18	SCLK	input	Serial clock logic input for accessing data and also the clock source for the conversion process.
19	CS	input	Active-low chip select input that initiates conversions and frames the serial data transfer.
20	A0	input	Multiplexer select logic input checked at the falling edge of CS: low selects Channel 1 of each ADC, high selects Channel 2.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-20
Category	Data Converters
Pins	20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Signal to Noise + Distortion	SINAD	68			dB	fIN = 300 kHz sine wave, fS = 1 MSPS	2
Total Harmonic Distortion	THD			-75	dB	fIN = 300 kHz sine wave, fS = 1 MSPS	2
Peak Harmonic or Spurious Noise	SFDR			-76	dB	fIN = 300 kHz sine wave, fS = 1 MSPS	2
Aperture Delay				10	ns		2
Aperture Delay Matching				200	ps		2
Integral Nonlinearity	INL	-1.5		1.5	LSB	A version; 0 V to 2 × VREF range	2
Differential Nonlinearity	DNL	-0.95		1.25	LSB	Guaranteed no missed codes to 12 bits	2
Offset Error		-8		8	LSB	0 V to VREF input range, straight binary	2
Gain Error		-2.5		2.5	LSB	0 V to VREF input range, straight binary	2
Positive Gain Error		-2.5		2.5	LSB	2 × VREF input range, twos complement	2
Zero Code Error		-8		8	LSB	2 × VREF input range, twos complement	2
Negative Gain Error		-2.5		2.5	LSB	2 × VREF input range, twos complement	2
Analog Input DC Leakage Current		-500		500	nA	TA = -40°C to +85°C	2
Analog Input DC Leakage Current				11	µA	85°C < TA ≤ 125°C	2
Reference Input Voltage Range		2		3	V	REF SELECT pin tied high	2
Reference DC Leakage Current		-30		30	µA	VREF pin	2
Reference DC Leakage Current		-160		160	µA	DCAPA, DCAPB pins	2
Reference Output Voltage		2.45		2.55	V		2
Logic Input Current	IIN	-1		1	µA	VIN = 0 V or VDRIVE	2
Logic Input Capacitance	CIN			10	pF		2
Output Low Voltage	VOL			0.4	V	ISINK = 200 µA	2
Floating-State Leakage Current		-1		1	µA	VDD = 2.7 V to 5.25 V	2
Floating-State Output Capacitance				10	pF		2
Track/Hold Acquisition Time				300	ns		3
Throughput Rate				1	MSPS	See Serial Interface section	3
Supply Voltage	VDD	2.7		5.25	V		3
Interface Supply Voltage	VDRIVE	2.7		5.25	V		3
IDD Normal Mode (Static)	IDD			3.1	mA	VDD = 4.75 V to 5.25 V; add 0.5 mA typical if using internal reference	3
IDD Normal Mode (Static)	IDD			2.8	mA	VDD = 2.7 V to 3.6 V; add 0.35 mA typical if using internal reference	3
IDD Operational	IDD			4.8	mA	fS = 1 MSPS, VDD = 4.75 V to 5.25 V; add 0.5 mA typical if using internal reference	3
IDD Operational	IDD			3.8	mA	fS = 1 MSPS, VDD = 2.7 V to 3.6 V; add 0.5 mA typical if using internal reference	3
IDD Partial Power-Down Mode	IDD			1.6	mA	fS = 100 kSPS, fSCLK = 20 MHz; add 0.2 mA typ if using internal reference	3
IDD Partial Power-Down Mode (Static)	IDD			560	µA	Static; add 100 µA typical if using internal reference	3
IDD Full Power-Down Mode	IDD			1	µA	SCLK on or off, TA = -40°C to +85°C	3
IDD Full Power-Down Mode	IDD			22	µA	SCLK on or off, 85°C < TA ≤ 125°C	3
Power Dissipation Normal Mode (Operational)				24	mW	VDD = 5 V	3
Power Dissipation Normal Mode (Operational)				11.4	mW	VDD = 3 V	3
Power Dissipation Partial Power-Down (Static)				2.8	mW	VDD = 5 V, SCLK on or off	3
Power Dissipation Partial Power-Down (Static)				1.68	mW	VDD = 3 V, SCLK on or off	3
Power Dissipation Full Power-Down (Static)				5	µW	VDD = 5 V, SCLK on or off	3
Power Dissipation Full Power-Down (Static)				33	µW	VDD = 3 V, SCLK on or off	3
SCLK Frequency	fSCLK	10			kHz		4
SCLK Frequency	fSCLK			20	MHz		4
Conversion Time	tCONVERT			800	ns	fSCLK = 20 MHz	4
Quiet Time	tQUIET			50	ns	Minimum time between end of serial read and next falling edge of CS	4
CS to SCLK Setup Time	t2	10			ns		4
Delay from CS until DOUTA and DOUTB Three-State Disabled	t3			25	ns		4
Data Access Time after SCLK Falling Edge	t4			40	ns	VDRIVE ≥ 3 V, CL = 50 pF; VDRIVE < 3 V, CL = 25 pF	4
SCLK to Data Valid Hold Time	t7	10			ns		4
CS Rising Edge to DOUTA, DOUTB High Impedance	t8			25	ns		4
SCLK Falling Edge to DOUTA, DOUTB High Impedance	t9	10		50	ns		4
AVDD to AGND		-0.3		7	V	TA = 25°C	5
DVDD to DGND		-0.3		7	V	TA = 25°C	5
Digital Input Voltage to DGND		-0.3		7	V	TA = 25°C	5
Input Current to Any Pin Except Supplies				10	mA	Transient currents of up to 100 mA will not cause SCR latch up	5
Operating Temperature Range		-40		125	°C	A, B versions	5
Storage Temperature Range		-65		150	°C		5
Junction Temperature				150	°C		5
TSSOP Package Power Dissipation				450	mW		5
Thermal Impedance Junction-to-Ambient	θJA		143		°C/W	TSSOP	5

CAD (KiCad official)

Symbol: AD7866ARUZ
Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
3D model: TSSOP-20 (KiCad packages3D, STEP)
3D model files: ad7866aruz-etched.step / ad7866aruz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7866aruz.step / ad7866aruz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (24 pp, sha256 97330acd060d2794, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD7866ARUZ

Verified AD7866ARUZ

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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