# AD7822BRUZ

**Analog Devices** · Analog To Digital Converters (ADCs) · TSSOP-20

AD7822BRUZ from Analog Devices, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DB2 | tri_state | Data output line 2, normally held in high impedance and driven when both RD and CS go active low. |
| 2 | DB1 | tri_state | Data output line 1, normally held in high impedance and driven when both RD and CS go active low. |
| 3 | DB0 | tri_state | Data output line 0 (LSB), normally held in high impedance and driven when both RD and CS go active low. |
| 4 | CONVST | input | Logic input; the falling edge starts an 8-bit conversion and places the track-and-hold in hold mode, and if low at the end of conversion the part powers down. |
| 5 | CS | input | Logic input chip select that enables the parallel port, needed when sharing a common data bus with another device. |
| 6 | RD | input | Logic input read signal that takes the output buffers out of high impedance, internally gated with CS so both must be low to enable the data bus. |
| 7 | DGND | power_in | Digital ground, the ground reference for digital circuitry. |
| 8 | EOC | output | Logic output end-of-conversion signal that can interrupt a microcontroller or latch data into a gate array when a conversion has finished. |
| 9 | PD | input | Logic input power-down pin; bringing it low places the part in power-down mode and it powers up when PD is brought high again. |
| 10 | NC | unconnected | No connect. |
| 11 | VIN1 | input | Analog input channel (single channel on the AD7822) with an input span of 2.5 V or 2 V depending on VDD, default range AGND to 2 V (VDD = 3 V ± 10%) or AGND to 2.5 V (VDD = 5 V ± 10%). |
| 12 | VMID | input | Used if connected to center the analog input span anywhere in the range AGND to VDD (default VMID 1 V at 3 V supply, 1.25 V at 5 V supply). |
| 13 | VREF IN/OUT | power_in | Analog input and output for an external reference or the on-chip 2.5 V reference; can be left unconnected or decoupled to AGND with a 0.1 µF capacitor when using the internal reference. |
| 14 | VDD | power_in | Positive supply voltage, 3 V ± 10% and 5 V ± 10%. |
| 15 | AGND | power_in | Analog ground, the ground reference for track-and-hold, comparators, reference circuit, and multiplexer. |
| 16 | DB7 | tri_state | Data output line 7 (MSB), normally held in high impedance and driven when both RD and CS go active low. |
| 17 | DB6 | tri_state | Data output line 6, normally held in high impedance and driven when both RD and CS go active low. |
| 18 | DB5 | tri_state | Data output line 5, normally held in high impedance and driven when both RD and CS go active low. |
| 19 | DB4 | tri_state | Data output line 4, normally held in high impedance and driven when both RD and CS go active low. |
| 20 | DB3 | tri_state | Data output line 3, normally held in high impedance and driven when both RD and CS go active low. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-20 |
| Category | Data Converters |
| Pins | 20 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Signal to (Noise + Distortion) Ratio | SINAD | 48 |  |  | dB | fIN = 30 kHz, fSAMPLE = 2 MHz | 3 |
| Total Harmonic Distortion | THD |  |  | -55 | dB | fIN = 30 kHz, fSAMPLE = 2 MHz | 3 |
| Peak Harmonic or Spurious Noise |  |  |  | -55 | dB | fIN = 30 kHz, fSAMPLE = 2 MHz | 3 |
| Integral Nonlinearity | INL | -0.75 |  | 0.75 | LSB |  | 3 |
| Differential Nonlinearity | DNL | -0.75 |  | 0.75 | LSB |  | 3 |
| Gain Error |  | -2 |  | 2 | LSB |  | 3 |
| Offset Error |  | -1 |  | 1 | LSB |  | 3 |
| Resolution |  |  | 8 |  | Bits |  | 3 |
| VIN Input Voltage (5 V) | VIN1 | 0 |  | 5.5 | V | VDD = 5 V ± 10%, input voltage span = 2.5 V; max printed as VDD | 3 |
| VMID Input Voltage (5 V) | VMID | 1.25 |  |  | V | VDD = 5 V ± 10%, default VMID = 1.25 V; max printed as VDD − 1.25 V | 3 |
| VMID Input Voltage (3 V) | VMID | 1 |  |  | V | VDD = 3 V ± 10%, default VMID = 1 V; max printed as VDD − 1 V | 3 |
| VIN Input Leakage Current |  | -1 |  | 1 | μA |  | 3 |
| VIN Input Capacitance |  |  |  | 15 | pF |  | 3 |
| VMID Input Impedance |  |  | 6 |  | kΩ |  | 3 |
| VREF IN/OUT Input Voltage Range | VREF IN/OUT | 2.45 |  | 2.55 | V | 2.5 V − 2% / 2.5 V + 2% | 3 |
| Reference Input Current |  |  | 1 | 100 | μA |  | 3 |
| On-chip Reference Error |  | -50 |  | 50 | mV | Nominal 2.5 V | 3 |
| On-chip Reference Temperature Coefficient |  |  | 50 |  | ppm/°C |  | 3 |
| Input High Voltage (5 V) | VINH | 2.4 |  |  | V | VDD = 5 V ± 10% | 3 |
| Input Low Voltage (5 V) | VINL |  |  | 0.8 | V | VDD = 5 V ± 10% | 3 |
| Input High Voltage (3 V) | VINH | 2 |  |  | V | VDD = 3 V ± 10% | 3 |
| Input Low Voltage (3 V) | VINL |  |  | 0.4 | V | VDD = 3 V ± 10% | 3 |
| Input Current | IIN | -1 |  | 1 | μA | 10 nA typical, VIN = 0 V to VDD | 3 |
| Input Capacitance | CIN |  |  | 10 | pF |  | 3 |
| Output High Voltage (5 V) | VOH | 4 |  |  | V | ISOURCE = 200 μA, VDD = 5 V ± 10% | 4 |
| Output High Voltage (3 V) | VOH | 2.4 |  |  | V | ISOURCE = 200 μA, VDD = 3 V ± 10% | 4 |
| Output Low Voltage (5 V) | VOL |  |  | 0.4 | V | ISINK = 200 μA, VDD = 5 V ± 10% | 4 |
| Output Low Voltage (3 V) | VOL |  |  | 0.2 | V | ISINK = 200 μA, VDD = 3 V ± 10% | 4 |
| High Impedance Leakage Current |  | -1 |  | 1 | μA |  | 4 |
| High Impedance Capacitance |  |  |  | 10 | pF |  | 4 |
| Track-and-Hold Acquisition Time |  |  |  | 200 | ns | See Circuit Description section | 4 |
| Conversion Time |  |  |  | 420 | ns |  | 4 |
| Power Supply Rejection |  | -1 |  | 1 | LSB | VDD ± 10% | 4 |
| Supply Voltage (5 V) | VDD | 4.5 |  | 5.5 | V | 5 V ± 10%; for specified performance | 4 |
| Supply Voltage (3 V) | VDD | 2.7 |  | 3.3 | V | 3 V ± 10%; for specified performance | 4 |
| Supply Current, Normal Operation | IDD |  | 8 | 12 | mA | Normal Operation | 4 |
| Supply Current, Power-Down | IDD |  | 0.2 | 5 | μA | Logic inputs = 0 V or VDD | 4 |
| Power Dissipation, Normal Operation |  |  | 24 | 36 | mW | VDD = 3 V | 4 |
| Power Dissipation, Power-Down 200 kSPS |  |  | 9.58 |  | mW | VDD = 3 V, 200 kSPS | 4 |
| Power Dissipation, Power-Down 500 kSPS |  |  | 23.94 |  | mW | VDD = 3 V, 500 kSPS | 4 |
| Conversion time | t1 |  |  | 420 | ns | Conversion time | 5 |
| Minimum CONVST pulse width | t2 | 20 |  |  | ns |  | 5 |
| Time between rising edge of RD and next falling edge of convert start | t3 | 30 |  |  | ns |  | 5 |
| EOC pulse width | t4 | 70 |  | 110 | ns |  | 5 |
| RD rising edge to EOC pulse high | t5 |  |  | 10 | ns |  | 5 |
| CS to RD setup time | t6 | 0 |  |  | ns |  | 5 |
| CS to RD hold time | t7 | 0 |  |  | ns |  | 5 |
| Minimum RD pulse width | t8 | 30 |  |  | ns |  | 5 |
| Data access time after RD low (5 V) | t9 |  |  | 10 | ns | 5 V ± 10% | 5 |
| Data access time after RD low (3 V) | t9 |  |  | 20 | ns | 3 V ± 10% | 5 |
| Bus relinquish time after RD high | t10 | 5 |  | 20 | ns |  | 5 |
| Address setup time before falling edge of RD | t11 | 10 |  |  | ns |  | 5 |
| Address hold time after falling edge of RD | t12 | 15 |  |  | ns |  | 5 |
| Time between new channel selection and convert start | t13 | 200 |  |  | ns |  | 5 |
| Power-up time, on-chip reference | tPOWER UP |  | 25 |  | μs | From rising edge of CONVST using on-chip reference | 5 |
| Power-up time, external reference | tPOWER UP |  |  | 1 | μs | From rising edge of CONVST using external 2.5 V reference | 5 |
| VDD to AGND | VDD | -0.3 |  | 7 | V | TA = 25°C | 6 |
| VDD to DGND | VDD | -0.3 |  | 7 | V | TA = 25°C | 6 |
| Analog Input Voltage to AGND | VIN1 to VIN8 | -0.3 |  |  | V | Max is VDD + 0.3 V | 6 |
| Operating Temperature Range |  | -40 |  | 85 | °C | Industrial (B Version) | 6 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 6 |
| Junction Temperature |  |  |  | 150 | °C |  | 6 |
| TSSOP Power Dissipation |  |  |  | 450 | mW | TSSOP Package | 6 |
| TSSOP Thermal Impedance | θJA |  | 128 |  | °C/W | TSSOP Package | 6 |

## CAD (KiCad official)

- Symbol: `AD7822BRUZ`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `ad7822bruz-etched.step` / `ad7822bruz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7822bruz.step` / `ad7822bruz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7822_7825_7829.pdf) (28 pp, sha256 `5957039edf3c2cfb`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad7822bruz-datasheet.pdf)