component
AD7799BRUZ
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADCs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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AD7799BRUZ
Analog Devices · Analog To Digital Converters (ADCs) · TSSOP-16
AD7799BRUZ from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCLK | input | Serial clock input for data transfers to and from the ADC, with a Schmitt-triggered input suitable for opto-isolated applications. |
| 2 | CS | input | Active-low chip select input used to select the ADC; it can be hardwired low for 3-wire operation. |
| 3 | AIN3(+)/P1 | passive | Positive terminal of differential analog input pair AIN3(+)/AIN3(−), or alternatively a general-purpose output bit referenced between AVDD and GND. |
| 4 | AIN3(−)/P2 | passive | Negative terminal of differential analog input pair AIN3(+)/AIN3(−), or alternatively a general-purpose output bit referenced between AVDD and GND. |
| 5 | AIN1(+) | passive | Positive terminal of differential analog input pair AIN1(+)/AIN1(−). |
| 6 | AIN1(−) | passive | Negative terminal of differential analog input pair AIN1(+)/AIN1(−). |
| 7 | AIN2(+) | passive | Positive terminal of differential analog input pair AIN2(+)/AIN2(−). |
| 8 | AIN2(−) | passive | Negative terminal of differential analog input pair AIN2(+)/AIN2(−). |
| 9 | REFIN(+) | input | Positive reference input that can lie between AVDD and GND + 0.1 V; the nominal REFIN(+) − REFIN(−) is 2.5 V and the part can use a reference from 0.1 V to AVDD. |
| 10 | REFIN(−) | input | Negative reference input that can lie between GND and AVDD − 0.1 V. |
| 11 | PSW | passive | Low-side power switch to GND. |
| 12 | GND | power_in | Ground reference point. |
| 13 | AVDD | power_in | Analog supply voltage, 2.7 V to 5.25 V. |
| 14 | DVDD | power_in | Digital interface supply voltage, 2.7 V to 5.25 V, which is independent of AVDD and sets the serial interface logic levels. |
| 15 | DOUT/RDY | output | Serial data output that also serves as a data ready output, going low to indicate conversion completion and going high again before the next update if data is not read. |
| 16 | DIN | input | Serial data input to the ADC input shift register, which transfers data to the control registers selected by the communication register bits. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16 |
| Category | Analog ICs |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| No Missing Codes | 24 | Bits | AD7799: fADC < 242 Hz | 3 | |||
| Integral Nonlinearity | -15 | 15 | ppm of FSR | 3 | |||
| Power Supply Rejection | 100 | dB | AIN = 1 V/gain, gain ≥ 4 | 3 | |||
| Absolute AIN Voltage, Unbuffered Mode (GND − 30 mV) | -30 | mV | Gain = 1 or 2 | 3 | |||
| Absolute AIN Voltage, Unbuffered Mode (AVDD + 30 mV) | 30 | mV | Gain = 1 or 2 | 3 | |||
| Absolute AIN Voltage, Buffered Mode (GND + 100 mV) | 100 | mV | Gain = 1 or 2 | 3 | |||
| Absolute AIN Voltage, Buffered Mode (AVDD − 100 mV) | -100 | mV | Gain = 1 or 2 | 3 | |||
| Absolute AIN Voltage, In-Amp Active (GND + 300 mV) | 300 | mV | Gain = 4 to 128 | 3 | |||
| Absolute AIN Voltage, In-Amp Active (AVDD − 1.1 V) | -1.1 | V | Gain = 4 to 128 | 3 | |||
| Common-Mode Voltage | VCM | 0.5 | V | VCM = (AIN(+) + AIN(−))/2, gain = 4 to 128 | 3 | ||
| Average Input Current, Buffered Mode or In-Amp Active | -1 | 1 | nA | Gain = 1 or 2, update rate < 100 Hz | 3 | ||
| Average Input Current, Buffered Mode or In-Amp Active | -250 | 250 | pA | Gain = 4 to 128, update rate < 100 Hz | 3 | ||
| Average Input Current, AIN3(+)/AIN3(−) | -1 | 1 | nA | update rate < 100 Hz | 3 | ||
| Normal Mode Rejection | 65 | dB | @ 50 Hz, 60 Hz; FS[3:0] = 1010 | 3 | |||
| Normal Mode Rejection | 80 | dB | @ 50 Hz; FS[3:0] = 1001 | 3 | |||
| Normal Mode Rejection | 90 | dB | @ 60 Hz; FS[3:0] = 1000 | 3 | |||
| Common-Mode Rejection | 100 | dB | @ DC; AIN = 1 V/gain, gain ≥ 4 | 3 | |||
| Full-Scale Calibration Limit | 1.05 | × FS | FS = full-scale analog input | 5 | |||
| Zero-Scale Calibration Limit | -1.05 | × FS | 5 | ||||
| Input Span | 0.8 | 2.1 | × FS | 5 | |||
| Power Supply Voltage, AVDD − GND | AVDD | 2.7 | 5.25 | V | 5 | ||
| Power Supply Voltage, DVDD − GND | DVDD | 2.7 | 5.25 | V | 5 | ||
| IDD Current | IDD | 140 | µA | Unbuffered mode | 5 | ||
| IDD Current | IDD | 180 | µA | Buffered mode, gain = 1 or 2 | 5 | ||
| IDD Current | IDD | 500 | µA | AD7799: gain = 4 to 128 | 5 | ||
| IDD (Power-Down Mode) | IDD | 1 | µA | 5 | |||
| Operating Temperature Range | -40 | 105 | °C | 5 | |||
| t3 SCLK High Pulse Width | t3 | 100 | ns | 6 | |||
| t4 SCLK Low Pulse Width | t4 | 100 | ns | 6 | |||
| t1 CS Falling Edge to DOUT/RDY Active Time | t1 | 0 | ns | 6 | |||
| t1 CS Falling Edge to DOUT/RDY Active Time | t1 | 60 | ns | DVDD = 4.75 V to 5.25 V | 6 | ||
| t1 CS Falling Edge to DOUT/RDY Active Time | t1 | 80 | ns | DVDD = 2.7 V to 3.6 V | 6 | ||
| t2 SCLK Active Edge to Data Valid Delay | t2 | 0 | ns | 6 | |||
| t2 SCLK Active Edge to Data Valid Delay | t2 | 60 | ns | DVDD = 4.75 V to 5.25 V | 6 | ||
| t2 SCLK Active Edge to Data Valid Delay | t2 | 80 | ns | DVDD = 2.7 V to 3.6 V | 6 | ||
| t5 Bus Relinquish Time After CS Inactive Edge | t5 | 10 | ns | 6 | |||
| t5 Bus Relinquish Time After CS Inactive Edge | t5 | 80 | ns | 6 | |||
| t6 SCLK Inactive Edge to CS Inactive Edge | t6 | 0 | ns | 6 | |||
| t7 SCLK Inactive Edge to DOUT/RDY High | t7 | 10 | ns | 6 | |||
| t8 CS Falling Edge to SCLK Active Edge Setup Time | t8 | 0 | ns | 6 | |||
| t9 Data Valid to SCLK Edge Setup Time | t9 | 30 | ns | 6 | |||
| t10 Data Valid to SCLK Edge Hold Time | t10 | 25 | ns | 6 | |||
| t11 CS Rising Edge to SCLK Edge Hold Time | t11 | 0 | ns | 6 | |||
| AVDD to GND | AVDD | -0.3 | 7 | V | 8 | ||
| DVDD to GND | DVDD | -0.3 | 7 | V | 8 | ||
| Analog Input Voltage to GND (max AVDD + 0.3 V) | -0.3 | V | 8 | ||||
| Reference Input Voltage to GND (max AVDD + 0.3 V) | -0.3 | V | 8 | ||||
| Digital Input Voltage to GND (max DVDD + 0.3 V) | -0.3 | V | 8 | ||||
| Digital Output Voltage to GND (max DVDD + 0.3 V) | -0.3 | V | 8 | ||||
| AIN/Digital Input Current | 10 | mA | 8 | ||||
| Operating Temperature Range | -40 | 105 | °C | 8 | |||
| Storage Temperature Range | -65 | 150 | °C | 8 | |||
| Maximum Junction Temperature | 150 | °C | 8 | ||||
| Lead Temperature, Soldering Reflow | 260 | °C | 8 | ||||
| Reference Input Voltage, REFIN(+) − REFIN(−) | 0.1 | V | Functional from 0.1 V to AVDD | 9 | |||
| Thermal Impedance, Junction-to-Ambient (TSSOP) | θJA | 128 | °C/W | 8 | |||
| Thermal Impedance, Junction-to-Case (TSSOP) | θJC | 14 | °C/W | 8 |
CAD (KiCad official)
- Symbol:
AD7799BRUZ - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
ad7799bruz-etched.step/ad7799bruz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7799bruz.step/ad7799bruz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (28 pp, sha256
8dc502708fc65462, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).