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AD7798BRUZ-REEL

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Analog Devices Analog To Digital Converters (ADC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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AD7798BRUZ-REEL

Analog Devices · Analog To Digital Converters (ADC) · TSSOP-16

AD7798BRUZ-REEL from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SCLK input Serial clock input with a Schmitt-triggered input for data transfers to and from the ADC, which can be continuous or noncontinuous.
2 CS input Active-low chip select input that selects the ADC on a multi-device bus and can be hardwired low for 3-wire operation.
3 AIN3(+)/P1 passive Positive terminal of the differential analog input pair AIN3(+)/AIN3(−), or alternatively a general-purpose output bit referenced between AVDD and GND.
4 AIN3(−)/P2 passive Negative terminal of the differential analog input pair AIN3(+)/AIN3(−), or alternatively a general-purpose output bit referenced between AVDD and GND.
5 AIN1(+) passive Positive terminal of the differential analog input pair AIN1(+)/AIN1(−).
6 AIN1(−) passive Negative terminal of the differential analog input pair AIN1(+)/AIN1(−).
7 AIN2(+) passive Positive terminal of the differential analog input pair AIN2(+)/AIN2(−).
8 AIN2(−) passive Negative terminal of the differential analog input pair AIN2(+)/AIN2(−).
9 REFIN(+) passive Positive reference input that can lie anywhere between AVDD and GND + 0.1 V, with a nominal REFIN(+) − REFIN(−) of 2.5 V and a usable reference range of 0.1 V to AVDD.
10 REFIN(−) passive Negative reference input that can lie anywhere between GND and AVDD − 0.1 V.
11 PSW output Low-side power switch to GND.
12 GND power_in Ground reference point for the device.
13 AVDD power_in Analog supply voltage of 2.7 V to 5.25 V.
14 DVDD power_in Digital interface supply of 2.7 V to 5.25 V that sets the serial interface logic levels and is independent of AVDD.
15 DOUT/RDY output Serial data output that also serves as a data-ready output, going low to indicate conversion completion, and is valid on the SCLK rising edge when CS is low.
16 DIN input Serial data input to the ADC input shift register, with register selection set by the communication register.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-16
Category Data Acquisition
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
No Missing Codes (AD7798) 16 Bits AD7798 3
Integral Nonlinearity -15 15 ppm of FSR 3
Power Supply Rejection 100 dB AIN = 1 V/gain, gain ≥ 4 3
Absolute AIN voltage, unbuffered mode, lower limit (GND − 30 mV) -30 mV Gain = 1 or 2 3
Absolute AIN voltage, unbuffered mode, upper limit (AVDD + 30 mV) 30 mV Gain = 1 or 2 3
Absolute AIN voltage, buffered mode, lower limit (GND + 100 mV) 100 mV Gain = 1 or 2 3
Absolute AIN voltage, buffered mode, upper limit (AVDD − 100 mV) -100 mV Gain = 1 or 2 3
Absolute AIN voltage, in-amp active, lower limit (GND + 300 mV) 300 mV Gain = 4 to 128 3
Absolute AIN voltage, in-amp active, upper limit (AVDD − 1.1 V) -1.1 V Gain = 4 to 128 3
Common-Mode Voltage, VCM VCM 0.5 V VCM = (AIN(+) + AIN(−))/2, gain = 4 to 128 3
Average Input Current, buffered mode or in-amp active -1 1 nA Gain = 1 or 2, update rate < 100 Hz 3
Average Input Current, buffered mode or in-amp active -250 250 pA Gain = 4 to 128, update rate < 100 Hz 3
Average Input Current, AIN3(+)/AIN3(−) -1 1 nA AIN3(+)/AIN3(−), update rate < 100 Hz 3
Normal Mode Rejection @ 50 Hz, 60 Hz 65 dB @ 50 Hz, 60 Hz; FS[3:0] = 1010 3
Normal Mode Rejection @ 50 Hz 80 dB @ 50 Hz; FS[3:0] = 1001 3
Normal Mode Rejection @ 60 Hz 90 dB @ 60 Hz; FS[3:0] = 1000 3
Common-Mode Rejection @ DC 100 dB AIN = 1 V/gain, gain ≥ 4 3
Common-Mode Rejection @ 50 Hz, 60 Hz 100 dB 50 ± 1 Hz, 60 ± 1 Hz; FS[3:0] = 1010 3
Full-Scale Calibration Limit 1.05 × FS FS = full-scale analog input 5
Zero-Scale Calibration Limit -1.05 × FS FS = full-scale analog input 5
Input Span, lower limit 0.8 × FS 5
Input Span, upper limit 2.1 × FS 5
Power Supply Voltage, AVDD − GND AVDD 2.7 5.25 V 5
Power Supply Voltage, DVDD − GND DVDD 2.7 5.25 V 5
Power Supply Current, unbuffered mode IDD 140 µA Unbuffered mode 5
Power Supply Current, buffered mode IDD 180 µA Buffered mode, gain = 1 or 2 5
Power Supply Current, AD7798 IDD 400 µA AD7798: gain = 4 to 128 5
Power Supply Current, power-down mode IDD 1 µA 5
SCLK high pulse width t3 100 ns 6
SCLK low pulse width t4 100 ns 6
CS falling edge to DOUT/RDY active time t1 0 ns 6
CS falling edge to DOUT/RDY active time t1 60 ns DVDD = 4.75 V to 5.25 V 6
CS falling edge to DOUT/RDY active time t1 80 ns DVDD = 2.7 V to 3.6 V 6
SCLK active edge to data valid delay t2 0 ns 6
SCLK active edge to data valid delay t2 60 ns DVDD = 4.75 V to 5.25 V 6
SCLK active edge to data valid delay t2 80 ns DVDD = 2.7 V to 3.6 V 6
Bus relinquish time after CS inactive edge t5 10 ns 6
Bus relinquish time after CS inactive edge t5 80 ns 6
SCLK inactive edge to CS inactive edge t6 0 ns 6
SCLK inactive edge to DOUT/RDY high t7 10 ns 6
CS falling edge to SCLK active edge setup time t8 0 ns 6
Data valid to SCLK edge setup time t9 30 ns 6
Data valid to SCLK edge hold time t10 25 ns 6
CS rising edge to SCLK edge hold time t11 0 ns 6
AVDD to GND -0.3 7 V 8
DVDD to GND -0.3 7 V 8
Analog Input Voltage to GND (upper bound AVDD + 0.3 V) -0.3 0.3 V Referenced to AVDD + 0.3 V 8
Reference Input Voltage to GND (upper bound AVDD + 0.3 V) -0.3 0.3 V Referenced to AVDD + 0.3 V 8
Digital Input Voltage to GND (upper bound DVDD + 0.3 V) -0.3 0.3 V Referenced to DVDD + 0.3 V 8
Digital Output Voltage to GND (upper bound DVDD + 0.3 V) -0.3 0.3 V Referenced to DVDD + 0.3 V 8
AIN/Digital Input Current 10 mA 8
Operating Temperature Range -40 105 °C 8
Storage Temperature Range -65 150 °C 8
Maximum Junction Temperature 150 °C 8
Lead Temperature, Soldering Reflow 260 °C Reflow 8
θJA Thermal Impedance (TSSOP) θJA 128 °C/W TSSOP 8
θJC Thermal Impedance (TSSOP) θJC 14 °C/W TSSOP 8

CAD (KiCad official)

  • Symbol: AD7798BRUZ-REEL
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: ad7798bruz-reel-etched.step / ad7798bruz-reel-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7798bruz-reel.step / ad7798bruz-reel.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (28 pp, sha256 8dc502708fc65462, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF