component
AD7794CRUZ
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADCs), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD7794CRUZ
Analog Devices · Analog To Digital Converters (ADCs) · TSSOP-24
AD7794CRUZ from Analog Devices, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCLK | input | Serial clock input for data transfers to and from the ADC, with a Schmitt-triggered input suitable for opto-isolated applications. |
| 2 | CLK | bidirectional | Clock in/clock out pin that makes the internal clock available or, when the internal clock is disabled, accepts an external clock to drive the ADC. |
| 3 | CS | input | Active-low chip select input used to select the ADC, which can be hardwired low for 3-wire operation. |
| 4 | NC | unconnected | No connect. |
| 5 | AIN6(+)/P1 | passive | Positive terminal of the differential analog input pair AIN6(+)/AIN6(−), which can also function as a general-purpose output bit referenced between AVDD and GND. |
| 6 | AIN6(−)/P2 | passive | Negative terminal of the differential analog input pair AIN6(+)/AIN6(−), which can also function as a general-purpose output bit referenced between AVDD and GND. |
| 7 | AIN1(+) | passive | Positive terminal of the differential analog input pair AIN1(+)/AIN1(−). |
| 8 | AIN1(−) | passive | Negative terminal of the differential analog input pair AIN1(+)/AIN1(−). |
| 9 | AIN2(+) | passive | Positive terminal of the differential analog input pair AIN2(+)/AIN2(−). |
| 10 | AIN2(−) | passive | Negative terminal of the differential analog input pair AIN2(+)/AIN2(−). |
| 11 | AIN3(+) | passive | Positive terminal of the differential analog input pair AIN3(+)/AIN3(−). |
| 12 | AIN3(−) | passive | Negative terminal of the differential analog input pair AIN3(+)/AIN3(−). |
| 13 | REFIN1(+) | passive | Positive reference input that can lie between AVDD and GND + 0.1 V, with a nominal REFIN1(+) − REFIN1(−) of 2.5 V and operation from 0.1 V to AVDD. |
| 14 | REFIN1(−) | passive | Negative reference input that can lie between GND and AVDD − 0.1 V. |
| 15 | AIN5(+)/IOUT2 | passive | Positive terminal of the differential analog input pair AIN5(+)/AIN5(−), which can alternatively be the programmable excitation current output (10 μA, 210 μA, or 1 mA). |
| 16 | AIN5(−)/IOUT1 | passive | Negative terminal of the differential analog input pair AIN5(+)/AIN5(−), which can alternatively be the programmable excitation current output (10 μA, 210 μA, or 1 mA). |
| 17 | AIN4(+)/REFIN2(+) | passive | Positive terminal of the differential analog input pair AIN4(+)/AIN4(−) and positive reference input for REFIN2, which can lie between AVDD and GND + 0.1 V. |
| 18 | AIN4(−)/REFIN2(−) | passive | Negative terminal of the differential analog input pair AIN4(+)/AIN4(−) and negative reference input for REFIN2, which can lie between GND and AVDD − 0.1 V. |
| 19 | PSW | passive | Low-side power switch to GND. |
| 20 | GND | power_in | Ground reference point for the device. |
| 21 | AVDD | power_in | Analog supply voltage, 2.7 V to 5.25 V. |
| 22 | DVDD | power_in | Serial interface supply voltage, 2.7 V to 5.25 V, independent of AVDD. |
| 23 | DOUT/RDY | output | Serial data output that also goes low to indicate conversion completion as a data ready output, with the data word placed on the SCLK falling edge when CS is low. |
| 24 | DIN | input | Serial data input to the ADC input shift register, which is transferred to the control registers as selected by the communications register bits. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-24 |
| Category | ADC/DAC/Data Conversion |
| Pins | 24 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| AVDD supply voltage (AVDD to GND) | AVDD | 2.7 | 5.25 | V | 7 | ||
| DVDD supply voltage (DVDD to GND) | DVDD | 2.7 | 5.25 | V | 7 | ||
| Power supply current IDD, unbuffered mode | IDD | 140 | μA | Unbuffered mode, external reference | 7 | ||
| Power supply current IDD, buffered mode | IDD | 185 | μA | Buffered mode, gain = 1 or 2, external reference | 7 | ||
| Power supply current IDD, gain 4 to 128, external reference | IDD | 400 | μA | Gain = 4 to 128, external reference | 7 | ||
| Power supply current IDD, gain 4 to 128, internal reference | IDD | 500 | μA | Gain = 4 to 128, internal reference | 7 | ||
| Power supply current IDD, power-down mode (AD7794C) | IDD | 2 | μA | Power-down mode, AD7794C | 7 | ||
| Integral nonlinearity | -15 | 15 | ppm of FSR | 3 | |||
| Power supply rejection | 100 | dB | AIN = 1 V/gain, gain ≥ 4, external reference | 3 | |||
| Absolute AIN voltage limit, unbuffered mode (min rel. GND, max rel. AVDD) | -30 | 30 | mV | Gain = 1 or 2; max = AVDD + 30 mV | 3 | ||
| Absolute AIN voltage limit, buffered mode (min rel. GND, max rel. AVDD) | 100 | -100 | mV | Gain = 1 or 2; max = AVDD − 100 mV | 3 | ||
| Absolute AIN voltage min, in-amp active (rel. GND) | 300 | mV | Gain = 4 to 128; min = GND + 300 mV; max = AVDD − 1.1 V (see review) | 3 | |||
| Average input current, gain 1 or 2, update rate < 100 Hz (AD7794C) | -3 | 3 | nA | Buffered mode or in-amp active; gain = 1 or 2, update rate < 100 Hz | 3 | ||
| Average input current, gain 4 to 128, update rate < 100 Hz (AD7794C) | -2 | 2 | nA | Buffered mode or in-amp active; gain = 4 to 128, update rate < 100 Hz | 3 | ||
| Average input current, AIN6(+)/AIN6(−) (AD7794C) | -3 | 3 | nA | AIN6(+)/AIN6(−) | 3 | ||
| Common-mode voltage, VCM (chop enabled) | VCM | 0.5 | V | VCM = (AIN(+) + AIN(−))/2, gain = 4 to 128 | 3 | ||
| Normal mode rejection, internal clock, 50 Hz and 60 Hz | 65 | dB | 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 | 3 | |||
| Normal mode rejection, internal clock, 50 Hz | 80 | dB | 50 ± 1 Hz, FS[3:0] = 1001 | 3 | |||
| Normal mode rejection, internal clock, 60 Hz | 90 | dB | 60 ± 1 Hz, FS[3:0] = 1000 | 3 | |||
| Internal reference initial accuracy (1.17 V) | -0.01 | 0.01 | % | AVDD = 4 V, TA = 25°C | 5 | ||
| Internal reference drift | 4 | 15 | ppm/°C | 5 | |||
| External REFIN voltage range, REFIN(+) − REFIN(−) | REFIN | 0.1 | V | Max is AVDD (see review) | 5 | ||
| Absolute REFIN voltage limits (min rel. GND, max rel. AVDD) | REFIN | -30 | 30 | mV | Max = AVDD + 30 mV | 5 | |
| Reference detect levels | 0.3 | 0.65 | V | NOXREF bit active if VREF < 0.3 V | 5 | ||
| IEXC output compliance, 10 μA or 210 μA (rel. AVDD) | IEXC1, IEXC2 | -0.65 | V | Current sources programmed to 10 μA or 210 μA; max = AVDD − 0.65 V | 5 | ||
| IEXC output compliance, 1 mA (rel. AVDD) | IEXC1, IEXC2 | -1.1 | V | Current sources programmed to 1 mA; max = AVDD − 1.1 V | 5 | ||
| IEXC output compliance, lower limit (rel. GND) | IEXC1, IEXC2 | -30 | mV | 5 | |||
| Low-side power switch on-resistance, AVDD = 5 V | RON | 7 | Ω | AVDD = 5 V | 6 | ||
| Low-side power switch on-resistance, AVDD = 3 V | RON | 9 | Ω | AVDD = 3 V | 6 | ||
| Low-side power switch allowable current | 30 | mA | Continuous current | 6 | |||
| Internal clock frequency tolerance (64 kHz nominal) | -3 | 3 | % | 64 kHz nominal, min/max | 6 | ||
| CS input low voltage, DVDD = 5 V | VINL | 0.8 | V | DVDD = 5 V | 6 | ||
| CS input low voltage, DVDD = 3 V | VINL | 0.4 | V | DVDD = 3 V | 6 | ||
| CS input high voltage | VINH | 2 | V | DVDD = 3 V or 5 V | 6 | ||
| SCLK/CLK/DIN Schmitt positive threshold, DVDD = 5 V (AD7794C) | VT(+) | 1.35 | 2.05 | V | DVDD = 5 V | 6 | |
| SCLK/CLK/DIN Schmitt negative threshold, DVDD = 5 V (AD7794C) | VT(−) | 0.8 | 1.9 | V | DVDD = 5 V | 6 | |
| SCLK/CLK/DIN Schmitt hysteresis, DVDD = 5 V (AD7794C) | VT(+) to VT(−) | 0.1 | 0.19 | V | DVDD = 5 V | 6 | |
| SCLK/CLK/DIN Schmitt positive threshold, DVDD = 3 V (AD7794C) | VT(+) | 0.9 | 2 | V | DVDD = 3 V | 6 | |
| SCLK/CLK/DIN Schmitt negative threshold, DVDD = 3 V (AD7794C) | VT(−) | 0.4 | 1.35 | V | DVDD = 3 V | 6 | |
| SCLK/CLK/DIN Schmitt hysteresis, DVDD = 3 V (AD7794C) | VT(+) to VT(−) | 0.06 | 0.15 | V | DVDD = 3 V | 6 | |
| Digital input current | IIN | -10 | 10 | μA | VIN = DVDD or GND | 6 | |
| Logic output VOH, DVDD = 3 V (rel. DVDD) | VOH | -0.6 | V | DVDD = 3 V, ISOURCE = 100 μA; min = DVDD − 0.6 V | 7 | ||
| Logic output VOL, DVDD = 3 V | VOL | 0.4 | V | DVDD = 3 V, ISINK = 100 μA | 7 | ||
| Logic output VOH, DVDD = 5 V | VOH | 4 | V | DVDD = 5 V, ISOURCE = 200 μA | 7 | ||
| Logic output VOL, DVDD = 5 V | VOL | 0.4 | V | DVDD = 5 V, ISINK = 1.6 mA (DOUT/RDY), 800 μA (CLK) | 7 | ||
| Full-scale calibration limit | 1.05 | × FS | 7 | ||||
| Zero-scale calibration limit | -1.05 | × FS | 7 | ||||
| System calibration input span | 0.8 | 2.1 | × FS | 7 | |||
| AVDD to GND (absolute maximum) | AVDD | -0.3 | 7 | V | 10 | ||
| DVDD to GND (absolute maximum) | DVDD | -0.3 | 7 | V | 10 | ||
| Analog input voltage to GND (absolute maximum) | -0.3 | 0.3 | V | Max is AVDD + 0.3 V (rel. AVDD) | 10 | ||
| Reference input voltage to GND (absolute maximum) | -0.3 | 0.3 | V | Max is AVDD + 0.3 V (rel. AVDD) | 10 | ||
| Digital input voltage to GND (absolute maximum) | -0.3 | 0.3 | V | Max is DVDD + 0.3 V (rel. DVDD) | 10 | ||
| Digital output voltage to GND (absolute maximum) | -0.3 | 0.3 | V | Max is DVDD + 0.3 V (rel. DVDD) | 10 | ||
| AIN/digital input current (absolute maximum) | 10 | mA | 10 | ||||
| Operating temperature range, C grade | TA | -40 | 125 | °C | C grade | 10 | |
| Storage temperature range | -65 | 150 | °C | 10 | |||
| Maximum junction temperature | 150 | °C | 10 | ||||
| Thermal impedance, junction to ambient (θJA) | θJA | 97.9 | °C/W | TSSOP | 10 | ||
| Thermal impedance, junction to case (θJC) | θJC | 14 | °C/W | TSSOP | 10 |
CAD (KiCad official)
- Symbol:
AD7794CRUZ - Footprint:
Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm - 3D model: TSSOP-24 (KiCad packages3D, STEP)
- 3D model files:
ad7794cruz-etched.step/ad7794cruz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7794cruz.step/ad7794cruz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (36 pp, sha256
01534278628e602c, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD7794CRUZ
**Analog Devices** · Analog To Digital Converters (ADCs) · TSSOP-24
AD7794CRUZ from Analog Devices, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCLK | input | Serial clock input for data transfers to and from the ADC, with a Schmitt-triggered input suitable for opto-isolated applications. |
| 2 | CLK | bidirectional | Clock in/clock out pin that makes the internal clock available or, when the internal clock is disabled, accepts an external clock to drive the ADC. |
| 3 | CS | input | Active-low chip select input used to select the ADC, which can be hardwired low for 3-wire operation. |
| 4 | NC | unconnected | No connect. |
| 5 | AIN6(+)/P1 | passive | Positive terminal of the differential analog input pair AIN6(+)/AIN6(−), which can also function as a general-purpose output bit referenced between AVDD and GND. |
| 6 | AIN6(−)/P2 | passive | Negative terminal of the differential analog input pair AIN6(+)/AIN6(−), which can also function as a general-purpose output bit referenced between AVDD and GND. |
| 7 | AIN1(+) | passive | Positive terminal of the differential analog input pair AIN1(+)/AIN1(−). |
| 8 | AIN1(−) | passive | Negative terminal of the differential analog input pair AIN1(+)/AIN1(−). |
| 9 | AIN2(+) | passive | Positive terminal of the differential analog input pair AIN2(+)/AIN2(−). |
| 10 | AIN2(−) | passive | Negative terminal of the differential analog input pair AIN2(+)/AIN2(−). |
| 11 | AIN3(+) | passive | Positive terminal of the differential analog input pair AIN3(+)/AIN3(−). |
| 12 | AIN3(−) | passive | Negative terminal of the differential analog input pair AIN3(+)/AIN3(−). |
| 13 | REFIN1(+) | passive | Positive reference input that can lie between AVDD and GND + 0.1 V, with a nominal REFIN1(+) − REFIN1(−) of 2.5 V and operation from 0.1 V to AVDD. |
| 14 | REFIN1(−) | passive | Negative reference input that can lie between GND and AVDD − 0.1 V. |
| 15 | AIN5(+)/IOUT2 | passive | Positive terminal of the differential analog input pair AIN5(+)/AIN5(−), which can alternatively be the programmable excitation current output (10 μA, 210 μA, or 1 mA). |
| 16 | AIN5(−)/IOUT1 | passive | Negative terminal of the differential analog input pair AIN5(+)/AIN5(−), which can alternatively be the programmable excitation current output (10 μA, 210 μA, or 1 mA). |
| 17 | AIN4(+)/REFIN2(+) | passive | Positive terminal of the differential analog input pair AIN4(+)/AIN4(−) and positive reference input for REFIN2, which can lie between AVDD and GND + 0.1 V. |
| 18 | AIN4(−)/REFIN2(−) | passive | Negative terminal of the differential analog input pair AIN4(+)/AIN4(−) and negative reference input for REFIN2, which can lie between GND and AVDD − 0.1 V. |
| 19 | PSW | passive | Low-side power switch to GND. |
| 20 | GND | power_in | Ground reference point for the device. |
| 21 | AVDD | power_in | Analog supply voltage, 2.7 V to 5.25 V. |
| 22 | DVDD | power_in | Serial interface supply voltage, 2.7 V to 5.25 V, independent of AVDD. |
| 23 | DOUT/RDY | output | Serial data output that also goes low to indicate conversion completion as a data ready output, with the data word placed on the SCLK falling edge when CS is low. |
| 24 | DIN | input | Serial data input to the ADC input shift register, which is transferred to the control registers as selected by the communications register bits. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-24 |
| Category | ADC/DAC/Data Conversion |
| Pins | 24 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| AVDD supply voltage (AVDD to GND) | AVDD | 2.7 | | 5.25 | V | | 7 |
| DVDD supply voltage (DVDD to GND) | DVDD | 2.7 | | 5.25 | V | | 7 |
| Power supply current IDD, unbuffered mode | IDD | | | 140 | μA | Unbuffered mode, external reference | 7 |
| Power supply current IDD, buffered mode | IDD | | | 185 | μA | Buffered mode, gain = 1 or 2, external reference | 7 |
| Power supply current IDD, gain 4 to 128, external reference | IDD | | | 400 | μA | Gain = 4 to 128, external reference | 7 |
| Power supply current IDD, gain 4 to 128, internal reference | IDD | | | 500 | μA | Gain = 4 to 128, internal reference | 7 |
| Power supply current IDD, power-down mode (AD7794C) | IDD | | | 2 | μA | Power-down mode, AD7794C | 7 |
| Integral nonlinearity | | -15 | | 15 | ppm of FSR | | 3 |
| Power supply rejection | | 100 | | | dB | AIN = 1 V/gain, gain ≥ 4, external reference | 3 |
| Absolute AIN voltage limit, unbuffered mode (min rel. GND, max rel. AVDD) | | -30 | | 30 | mV | Gain = 1 or 2; max = AVDD + 30 mV | 3 |
| Absolute AIN voltage limit, buffered mode (min rel. GND, max rel. AVDD) | | 100 | | -100 | mV | Gain = 1 or 2; max = AVDD − 100 mV | 3 |
| Absolute AIN voltage min, in-amp active (rel. GND) | | 300 | | | mV | Gain = 4 to 128; min = GND + 300 mV; max = AVDD − 1.1 V (see review) | 3 |
| Average input current, gain 1 or 2, update rate < 100 Hz (AD7794C) | | -3 | | 3 | nA | Buffered mode or in-amp active; gain = 1 or 2, update rate < 100 Hz | 3 |
| Average input current, gain 4 to 128, update rate < 100 Hz (AD7794C) | | -2 | | 2 | nA | Buffered mode or in-amp active; gain = 4 to 128, update rate < 100 Hz | 3 |
| Average input current, AIN6(+)/AIN6(−) (AD7794C) | | -3 | | 3 | nA | AIN6(+)/AIN6(−) | 3 |
| Common-mode voltage, VCM (chop enabled) | VCM | 0.5 | | | V | VCM = (AIN(+) + AIN(−))/2, gain = 4 to 128 | 3 |
| Normal mode rejection, internal clock, 50 Hz and 60 Hz | | 65 | | | dB | 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 | 3 |
| Normal mode rejection, internal clock, 50 Hz | | 80 | | | dB | 50 ± 1 Hz, FS[3:0] = 1001 | 3 |
| Normal mode rejection, internal clock, 60 Hz | | 90 | | | dB | 60 ± 1 Hz, FS[3:0] = 1000 | 3 |
| Internal reference initial accuracy (1.17 V) | | -0.01 | | 0.01 | % | AVDD = 4 V, TA = 25°C | 5 |
| Internal reference drift | | | 4 | 15 | ppm/°C | | 5 |
| External REFIN voltage range, REFIN(+) − REFIN(−) | REFIN | 0.1 | | | V | Max is AVDD (see review) | 5 |
| Absolute REFIN voltage limits (min rel. GND, max rel. AVDD) | REFIN | -30 | | 30 | mV | Max = AVDD + 30 mV | 5 |
| Reference detect levels | | 0.3 | | 0.65 | V | NOXREF bit active if VREF < 0.3 V | 5 |
| IEXC output compliance, 10 μA or 210 μA (rel. AVDD) | IEXC1, IEXC2 | | | -0.65 | V | Current sources programmed to 10 μA or 210 μA; max = AVDD − 0.65 V | 5 |
| IEXC output compliance, 1 mA (rel. AVDD) | IEXC1, IEXC2 | | | -1.1 | V | Current sources programmed to 1 mA; max = AVDD − 1.1 V | 5 |
| IEXC output compliance, lower limit (rel. GND) | IEXC1, IEXC2 | -30 | | | mV | | 5 |
| Low-side power switch on-resistance, AVDD = 5 V | RON | | | 7 | Ω | AVDD = 5 V | 6 |
| Low-side power switch on-resistance, AVDD = 3 V | RON | | | 9 | Ω | AVDD = 3 V | 6 |
| Low-side power switch allowable current | | | | 30 | mA | Continuous current | 6 |
| Internal clock frequency tolerance (64 kHz nominal) | | -3 | | 3 | % | 64 kHz nominal, min/max | 6 |
| CS input low voltage, DVDD = 5 V | VINL | | | 0.8 | V | DVDD = 5 V | 6 |
| CS input low voltage, DVDD = 3 V | VINL | | | 0.4 | V | DVDD = 3 V | 6 |
| CS input high voltage | VINH | 2 | | | V | DVDD = 3 V or 5 V | 6 |
| SCLK/CLK/DIN Schmitt positive threshold, DVDD = 5 V (AD7794C) | VT(+) | 1.35 | | 2.05 | V | DVDD = 5 V | 6 |
| SCLK/CLK/DIN Schmitt negative threshold, DVDD = 5 V (AD7794C) | VT(−) | 0.8 | | 1.9 | V | DVDD = 5 V | 6 |
| SCLK/CLK/DIN Schmitt hysteresis, DVDD = 5 V (AD7794C) | VT(+) to VT(−) | 0.1 | | 0.19 | V | DVDD = 5 V | 6 |
| SCLK/CLK/DIN Schmitt positive threshold, DVDD = 3 V (AD7794C) | VT(+) | 0.9 | | 2 | V | DVDD = 3 V | 6 |
| SCLK/CLK/DIN Schmitt negative threshold, DVDD = 3 V (AD7794C) | VT(−) | 0.4 | | 1.35 | V | DVDD = 3 V | 6 |
| SCLK/CLK/DIN Schmitt hysteresis, DVDD = 3 V (AD7794C) | VT(+) to VT(−) | 0.06 | | 0.15 | V | DVDD = 3 V | 6 |
| Digital input current | IIN | -10 | | 10 | μA | VIN = DVDD or GND | 6 |
| Logic output VOH, DVDD = 3 V (rel. DVDD) | VOH | -0.6 | | | V | DVDD = 3 V, ISOURCE = 100 μA; min = DVDD − 0.6 V | 7 |
| Logic output VOL, DVDD = 3 V | VOL | | | 0.4 | V | DVDD = 3 V, ISINK = 100 μA | 7 |
| Logic output VOH, DVDD = 5 V | VOH | 4 | | | V | DVDD = 5 V, ISOURCE = 200 μA | 7 |
| Logic output VOL, DVDD = 5 V | VOL | | | 0.4 | V | DVDD = 5 V, ISINK = 1.6 mA (DOUT/RDY), 800 μA (CLK) | 7 |
| Full-scale calibration limit | | | | 1.05 | × FS | | 7 |
| Zero-scale calibration limit | | -1.05 | | | × FS | | 7 |
| System calibration input span | | 0.8 | | 2.1 | × FS | | 7 |
| AVDD to GND (absolute maximum) | AVDD | -0.3 | | 7 | V | | 10 |
| DVDD to GND (absolute maximum) | DVDD | -0.3 | | 7 | V | | 10 |
| Analog input voltage to GND (absolute maximum) | | -0.3 | | 0.3 | V | Max is AVDD + 0.3 V (rel. AVDD) | 10 |
| Reference input voltage to GND (absolute maximum) | | -0.3 | | 0.3 | V | Max is AVDD + 0.3 V (rel. AVDD) | 10 |
| Digital input voltage to GND (absolute maximum) | | -0.3 | | 0.3 | V | Max is DVDD + 0.3 V (rel. DVDD) | 10 |
| Digital output voltage to GND (absolute maximum) | | -0.3 | | 0.3 | V | Max is DVDD + 0.3 V (rel. DVDD) | 10 |
| AIN/digital input current (absolute maximum) | | | | 10 | mA | | 10 |
| Operating temperature range, C grade | TA | -40 | | 125 | °C | C grade | 10 |
| Storage temperature range | | -65 | | 150 | °C | | 10 |
| Maximum junction temperature | | | | 150 | °C | | 10 |
| Thermal impedance, junction to ambient (θJA) | θJA | | 97.9 | | °C/W | TSSOP | 10 |
| Thermal impedance, junction to case (θJC) | θJC | | 14 | | °C/W | TSSOP | 10 |
## CAD (KiCad official)
- Symbol: `AD7794CRUZ`
- Footprint: `Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm`
- 3D model: TSSOP-24 (KiCad packages3D, STEP)
- 3D model files: `ad7794cruz-etched.step` / `ad7794cruz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7794cruz.step` / `ad7794cruz.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7794_7795.pdf) (36 pp, sha256 `01534278628e602c`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad7794cruz-datasheet.pdf)