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AD7789BRMZ-REEL
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Analog Devices Analog To Digital Converters (ADC), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAD7789BRMZ-REEL
Analog Devices · Analog To Digital Converters (ADC) · MSOP-10
AD7789BRMZ-REEL from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCLK | input | Serial clock input for data transfers to and from the ADC, with a Schmitt-triggered input that suits opto-isolated applications and may be continuous or noncontinuous. |
| 2 | CS | input | Active-low chip select input used to select the ADC on a shared serial bus or as a frame sync, and it can be hardwired low for 3-wire operation. |
| 3 | AIN(+) | input | Positive terminal of the fully differential analog input. |
| 4 | AIN(-) | input | Negative terminal of the fully differential analog input. |
| 5 | REFIN(+) | input | Positive reference input that can lie anywhere between VDD and GND + 0.1 V, with a nominal REFIN(+) − REFIN(−) of 2.5 V and operation from 0.1 V to VDD. |
| 6 | REFIN(-) | input | Negative reference input that can lie anywhere between GND and VDD − 0.1 V. |
| 7 | GND | power_in | Ground reference point for the device. |
| 8 | VDD | power_in | Supply voltage, 3 V or 5 V nominal (the device operates from 2.5 V to 5.25 V per the features list). |
| 9 | DOUT/RDY | tri_state | Serial data output and ready flag whose falling edge can interrupt a processor to indicate valid data; it is three-stated when CS is high while the RDY bit stays active in the status register. |
| 10 | DIN | input | Serial data input to the ADC input shift register, which is transferred to the internal control registers as selected by the communications register. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-10 |
| Category | Data Acquisition |
| Pins | 10 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| No Missing Codes | 24 | Bits | 3 | ||||
| Integral Nonlinearity | -15 | 15 | ppm of FSR | 3 | |||
| Power Supply Rejection | 90 | dB | AIN = 1 V | 3 | |||
| Absolute AIN Voltage Limits (lower) | -30 | mV | Printed as GND − 30 mV | 3 | |||
| Absolute AIN Voltage Limits (upper) | 30 | mV | Printed as VDD + 30 mV | 3 | |||
| Normal-Mode Rejection (AIN) | 65 | dB | 50 Hz ± 1 Hz, 60 Hz ± 1 Hz | 3 | |||
| Common-Mode Rejection at DC | 90 | dB | AIN = 1 V; at DC | 3 | |||
| Common-Mode Rejection at 50 Hz, 60 Hz | 100 | dB | AIN = 1 V; 50 Hz ± 1 Hz, 60 Hz ± 1 Hz | 3 | |||
| Reference Voltage Range | 0.1 | V | 3 | ||||
| Absolute REFIN Voltage Limits (lower) | -30 | mV | Printed as GND − 30 mV | 3 | |||
| Absolute REFIN Voltage Limits (upper) | 30 | mV | Printed as VDD + 30 mV | 3 | |||
| Normal-Mode Rejection (REFIN) | 65 | dB | 50 Hz ± 1 Hz, 60 Hz ± 1 Hz | 3 | |||
| Input Low Voltage | VINL | 0.8 | V | VDD = 5 V | 5 | ||
| Input Low Voltage | VINL | 0.4 | V | VDD = 3 V | 5 | ||
| Input High Voltage | VINH | 2 | V | VDD = 3 V or 5 V | 5 | ||
| SCLK Positive Threshold | VT(+) | 1.4 | 2 | V | VDD = 5 V | 5 | |
| SCLK Negative Threshold | VT(−) | 0.8 | 1.4 | V | VDD = 5 V | 5 | |
| SCLK Hysteresis | VT(+) − VT(−) | 0.3 | 0.85 | V | VDD = 5 V | 5 | |
| SCLK Positive Threshold | VT(+) | 0.9 | 2 | V | VDD = 3 V | 5 | |
| SCLK Negative Threshold | VT(−) | 0.4 | 1.1 | V | VDD = 3 V | 5 | |
| Input Currents | -1 | 1 | µA | VIN = VDD | 5 | ||
| Output High Voltage | VOH | -0.6 | V | Printed as VDD − 0.6 V; VDD = 3 V, ISOURCE = 100 µA | 5 | ||
| Output Low Voltage | VOL | 0.4 | V | VDD = 3 V, ISINK = 100 µA | 5 | ||
| Output High Voltage | VOH | 4 | V | VDD = 5 V, ISOURCE = 200 µA | 5 | ||
| Floating-State Leakage Current | -1 | 1 | µA | 5 | |||
| Power Supply Voltage | VDD | 2.5 | 5.25 | V | AD7789B grade | 5 | |
| Power Supply Current | IDD | 75 | µA | 5 | |||
| Power Supply Current | IDD | 80 | µA | 5 | |||
| Power-Down Mode Current | IDD | 1 | µA | 5 | |||
| SCLK high pulse width | t3 | 100 | ns | 6 | |||
| SCLK low pulse width | t4 | 100 | ns | 6 | |||
| CS falling edge to DOUT/RDY active time | t1 | 0 | ns | 6 | |||
| CS falling edge to DOUT/RDY active time | t1 | 60 | ns | VDD = 4.75 V to 5.25 V | 6 | ||
| CS falling edge to DOUT/RDY active time | t1 | 80 | ns | VDD = 2.7 V to 3.6 V | 6 | ||
| SCLK active edge to data valid delay | t2 | 0 | ns | 6 | |||
| SCLK active edge to data valid delay | t2 | 60 | ns | VDD = 4.75 V to 5.25 V | 6 | ||
| SCLK active edge to data valid delay | t2 | 80 | ns | VDD = 2.7 V to 3.6 V | 6 | ||
| Bus relinquish time after CS inactive edge | t5 | 10 | ns | 6 | |||
| Bus relinquish time after CS inactive edge | t5 | 80 | ns | 6 | |||
| SCLK inactive edge to CS inactive edge | t6 | 0 | ns | 6 | |||
| SCLK inactive edge to DOUT/RDY high | t7 | 10 | ns | 6 | |||
| CS falling edge to SCLK active edge setup time | t8 | 0 | ns | 6 | |||
| Data valid to SCLK edge setup time | t9 | 30 | ns | 6 | |||
| Data valid to SCLK edge hold time | t10 | 25 | ns | 6 | |||
| CS rising edge to SCLK edge hold time | t11 | 0 | ns | 6 | |||
| VDD to GND | VDD | -0.3 | 7 | V | 8 | ||
| Analog Input Voltage to GND | -0.3 | V | Upper limit printed as VDD + 0.3 V | 8 | |||
| Reference Input Voltage to GND | -0.3 | V | Upper limit printed as VDD + 0.3 V | 8 | |||
| Total AIN/REFIN Current | 30 | mA | Indefinite | 8 | |||
| Digital Input Voltage to GND | -0.3 | V | Upper limit printed as VDD + 0.3 V | 8 | |||
| Digital Output Voltage to GND | -0.3 | V | Upper limit printed as VDD + 0.3 V | 8 | |||
| Operating Temperature Range | TA | -40 | 105 | °C | B grade | 8 | |
| Storage Temperature Range | -65 | 150 | °C | 8 | |||
| Maximum Junction Temperature | TJ | 150 | °C | 8 | |||
| Thermal Impedance, junction-to-ambient | θJA | 206 | °C/W | 10-Lead MSOP | 8 | ||
| Thermal Impedance, junction-to-case | θJC | 44 | °C/W | 10-Lead MSOP | 8 | ||
| Lead Temperature, Soldering | 300 | °C | 10 sec | 8 | |||
| IR Reflow, Peak Temperature | 220 | °C | 8 |
CAD (KiCad official)
- Symbol:
AD7789BRMZ-REEL - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files:
ad7789brmz-reel-etched.step/ad7789brmz-reel-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7789brmz-reel.step/ad7789brmz-reel.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (20 pp, sha256
9e6583b1d795c746, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).