component
AD7785BRUZ
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADCs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 3d ago |
| viewers | 3d ago |
| ad7785bruz-etched.glb | 3d ago |
| ad7785bruz-etched.step | 3d ago |
| ad7785bruz-hero.glb | 3d ago |
| ad7785bruz-hero.overlay.json | 3d ago |
| ad7785bruz.glb | 3d ago |
| ad7785bruz.kicad_mod | 3d ago |
| ad7785bruz.kicad_sym | 3d ago |
| ad7785bruz.lbr | 3d ago |
| ad7785bruz.step | 3d ago |
| package.json | 3d ago |
| page.json | 3d ago |
| README.md | 3d ago |
| verification.json | 3d ago |
AD7785BRUZ
Analog Devices · Analog To Digital Converters (ADCs) · TSSOP-16
AD7785BRUZ from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCLK | input | Serial clock input for data transfers to and from the ADC, with a Schmitt-triggered input suitable for opto-isolated applications; it can be continuous or noncontinuous. |
| 2 | CLK | bidirectional | Clock in/clock out pin where the internal clock can be made available or the internal clock disabled so the ADC is driven by an external clock. |
| 3 | CS | input | Active-low chip select input used to select the ADC on a shared serial bus or as a frame synchronization signal, and it can be hardwired low for 3-wire mode. |
| 4 | IOUT1 | output | Output of the internal excitation current source, programmable to 10 μA, 210 μA, or 1 mA, with either IEXC1 or IEXC2 switchable to this pin. |
| 5 | AIN1(+) | input | Analog input that is the positive terminal of differential pair AIN1(+)/AIN1(−). |
| 6 | AIN1(−) | input | Analog input that is the negative terminal of differential pair AIN1(+)/AIN1(−). |
| 7 | AIN2(+) | input | Analog input that is the positive terminal of differential pair AIN2(+)/AIN2(−). |
| 8 | AIN2(−) | input | Analog input that is the negative terminal of differential pair AIN2(+)/AIN2(−). |
| 9 | REFIN(+)/AIN3(+) | input | Positive reference input (anywhere between AVDD and GND + 0.1 V, nominal 2.5 V reference, functional from 0.1 V to AVDD) or positive analog input AIN3(+). |
| 10 | REFIN(−)/AIN3(−) | input | Negative reference input that can lie anywhere between GND and AVDD − 0.1 V, or negative analog input AIN3(−). |
| 11 | IOUT2 | output | Output of the internal excitation current source, programmable to 10 μA, 210 μA, or 1 mA, with either IEXC1 or IEXC2 switchable to this pin. |
| 12 | GND | power_in | Ground reference point. |
| 13 | AVDD | power_in | Supply voltage, 2.7 V to 5.25 V. |
| 14 | DVDD | power_in | Digital interface supply voltage between 2.7 V and 5.25 V, independent of the AVDD voltage, setting the logic levels of the serial interface pins. |
| 15 | DOUT/RDY | output | Serial data output for the on-chip registers and data ready indicator that goes low when a conversion completes, with data placed on the SCLK falling edge when CS is low. |
| 16 | DIN | input | Serial data input to the input shift register, whose contents are transferred to the control registers selected by the communications register bits. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16 |
| Category | Data Converters |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| No Missing Codes | 20 | Bits | 3 | ||||
| Integral Nonlinearity | INL | 15 | ppm of FSR | 3 | |||
| Power Supply Rejection | 100 | dB | AIN = 1 V/gain, gain ≥ 4, external reference | 3 | |||
| Absolute AIN Voltage Lower Limit, Unbuffered | -0.03 | V | Gain = 1 or 2; GND, 30 mV | 3 | |||
| Absolute AIN Voltage Upper Limit, Unbuffered | 0.03 | V | Gain = 1 or 2; AVDD + 30 mV | 3 | |||
| Common-Mode Voltage | VCM | 0.5 | V | VCM = (AIN(+) + AIN(−))/2, gain = 4 to 128 | 3 | ||
| Average Input Current, Buffered | -1 | 1 | nA | Gain = 1 or 2, update rate < 100 Hz | 3 | ||
| Average Input Current, In-Amp | -250 | 250 | pA | Gain = 4 to 128, update rate < 100 Hz | 3 | ||
| Normal Mode Rejection, Internal Clock @ 50/60 Hz | 65 | 80 | dB | 50 ± 1 Hz, 60 ± 1 Hz, FS[3:0] = 1010 | 3 | ||
| Common-Mode Rejection @ DC | 100 | dB | AIN = 1 V/gain, gain ≥ 4 | 3 | |||
| Internal Reference Initial Accuracy | -0.01 | 1.17 | 0.01 | % | AVDD = 4 V, TA = 25°C; typ is 1.17 V | 4 | |
| Internal Reference Drift | 4 | 15 | ppm/°C | 4 | |||
| Reference Voltage Range | 0.1 | V | Upper limit AVDD | 4 | |||
| Logic Input Low Voltage CS | VINL | 0.8 | V | DVDD = 5 V | 4 | ||
| Logic Input Low Voltage CS | VINL | 0.4 | V | DVDD = 3 V | 4 | ||
| Logic Input High Voltage CS | VINH | 2 | V | DVDD = 3 V or 5 V | 4 | ||
| Input Currents | -10 | 10 | μA | VIN = DVDD or GND | 5 | ||
| Output High Voltage | VOH | 4 | V | DVDD = 5 V, ISOURCE = 200 μA | 5 | ||
| Output Low Voltage | VOL | 0.4 | V | DVDD = 5 V, ISINK = 1.6 mA (DOUT/RDY)/800 μA (CLK) | 5 | ||
| Floating-State Leakage Current | -10 | 10 | μA | 5 | |||
| AVDD Supply Voltage | AVDD | 2.7 | 5.25 | V | AVDD to GND | 5 | |
| DVDD Supply Voltage | DVDD | 2.7 | 5.25 | V | DVDD to GND | 5 | |
| IDD Current | IDD | 110 | 140 | μA | unbuffered mode, external reference; typ @ AVDD = 3 V | 5 | |
| IDD Current | IDD | 300 | 400 | μA | gain = 4 to 128, external reference; typ @ AVDD = 3 V | 5 | |
| IDD Current | IDD | 400 | 500 | μA | gain = 4 to 128, internal reference; typ @ AVDD = 3 V | 5 | |
| IDD (Power-Down Mode) | IDD | 1 | μA | 5 | |||
| SCLK high pulse width | t3 | 100 | ns | 6 | |||
| SCLK low pulse width | t4 | 100 | ns | 6 | |||
| CS falling edge to DOUT/RDY active time | t1 | 0 | 60 | ns | DVDD = 4.75 V to 5.25 V | 6 | |
| SCLK active edge to data valid delay | t2 | 0 | 60 | ns | DVDD = 4.75 V to 5.25 V | 6 | |
| Bus relinquish time after CS inactive edge | t5 | 10 | 80 | ns | 6 | ||
| Data valid to SCLK edge setup time | t9 | 30 | ns | 6 | |||
| Data valid to SCLK edge hold time | t10 | 25 | ns | 6 | |||
| AVDD to GND | AVDD | -0.3 | 7 | V | TA = 25°C | 8 | |
| DVDD to GND | DVDD | -0.3 | 7 | V | TA = 25°C | 8 | |
| AIN/Digital Input Current | 10 | mA | TA = 25°C | 8 | |||
| Operating Temperature Range | -40 | 105 | °C | 8 | |||
| Storage Temperature Range | -65 | 150 | °C | 8 | |||
| Maximum Junction Temperature | TJ | 150 | °C | 8 | |||
| Thermal Impedance Junction-to-Ambient | θJA | 150.4 | °C/W | TSSOP | 8 | ||
| Thermal Impedance Junction-to-Case | θJC | 27.6 | °C/W | TSSOP | 8 |
CAD (KiCad official)
- Symbol:
AD7785BRUZ - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
ad7785bruz-etched.step/ad7785bruz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7785bruz.step/ad7785bruz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (32 pp, sha256
5933a37f877fb4ee, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).