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AD7782BRUZ

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Analog Devices Analog To Digital Converters (ADCs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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AD7782BRUZ

Analog Devices · Analog To Digital Converters (ADCs) · TSSOP-16

AD7782BRUZ from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 XTAL1 input Input to the 32.768 kHz crystal oscillator inverter, used with a 32.768 kHz watch crystal.
2 REFIN(+) input Positive reference input that can lie anywhere between VDD and GND +1 V, with a nominal REFIN(+) - REFIN(-) of 2.5 V and operation from 1 V to VDD.
3 REFIN(-) input Negative reference input that can lie anywhere between GND and VDD - 1 V.
4 AIN1(+) input Positive terminal of the fully-differential analog input pair AIN1(+)/AIN1(-), with absolute input voltage limits of GND + 100 mV to VDD - 100 mV.
5 AIN1(-) input Negative terminal of the fully-differential analog input pair AIN1(+)/AIN1(-), with absolute input voltage limits of GND + 100 mV to VDD - 100 mV.
6 AIN2(+) input Positive terminal of the fully-differential analog input pair AIN2(+)/AIN2(-), with absolute input voltage limits of GND + 100 mV to VDD - 100 mV.
7 AIN2(-) input Negative terminal of the fully-differential analog input pair AIN2(+)/AIN2(-), with absolute input voltage limits of GND + 100 mV to VDD - 100 mV.
8 CH1/CH2 input Channel select logic input where CH1/CH2 = 0 selects AIN1(+)/AIN1(-) and CH1/CH2 = 1 selects AIN2(+)/AIN2(-).
9 RANGE input Logic input configuring the PGA input range, where RANGE = 0 gives ±160 mV and RANGE = 1 gives ±2.56 V for a +2.5 V reference.
10 SCLK bidirectional Serial clock that is an output in master mode with one SCLK period equal to one XTAL period, and a Schmitt-triggered input in slave mode.
11 CS input Active-low chip select which, when taken high, aborts the conversion, three-states DOUT and SCLK, and places the part in standby mode.
12 DOUT/RDY output Serial data output and data-ready output that goes low when valid data is available and outputs data on the falling SCLK edge, valid on the rising edge.
13 MODE input Selects the operating mode, with MODE = 0 for master mode and MODE = 1 for slave mode.
14 GND power_in Ground reference point for the AD7782.
15 VDD power_in Supply voltage of 3 V or 5 V nominal, specified for 2.7 V to 3.6 V or 4.75 V to 5.25 V.
16 XTAL2 output Output from the 32.768 kHz crystal oscillator inverter.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-16
Category Data Converters
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
No Missing Codes 24 Bits 2
Integral Nonlinearity 10 ppm of FSR 2
Normal-Mode Rejection @ 50 Hz 60 dB 50 Hz ± 1 Hz 2
Normal-Mode Rejection @ 60 Hz 94 dB 60 Hz ± 1 Hz 2
Common-Mode Rejection @ DC 105 dB Input Range = ±160 mV, VIN = 1/16 V 2
Common-Mode Rejection @ 50 Hz 100 dB 50 Hz ± 1 Hz 2
Common-Mode Rejection @ 60 Hz 100 dB 60 Hz ± 1 Hz 2
DC Input Current -1 1 nA 2
REFIN Voltage Range 1 V 2
Normal-Mode Rejection (reference) @ 50 Hz 60 dB 50 Hz ± 1 Hz 2
Normal-Mode Rejection (reference) @ 60 Hz 94 dB 60 Hz ± 1 Hz 2
Input Low Voltage VINL 0.8 V VDD = 5 V 2
Input Low Voltage VINL 0.4 V VDD = 3 V 2
Input High Voltage VINH 2 V VDD = 3 V or 5 V 2
Schmitt Positive Threshold VT(+) 1.4 2 V VDD = 5 V 2
Schmitt Negative Threshold VT(-) 0.8 1.4 V VDD = 5 V 2
Schmitt Hysteresis VT(+), VT(-) 0.3 0.85 V VDD = 5 V 2
Schmitt Positive Threshold VT(+) 0.95 2 V VDD = 3 V 2
Schmitt Negative Threshold VT(-) 0.4 1.1 V VDD = 3 V 2
XTAL1 Input Low Voltage VINL 0.8 V VDD = 5 V 3
XTAL1 Input High Voltage VINH 3.5 V VDD = 5 V 3
XTAL1 Input Low Voltage VINL 0.4 V VDD = 3 V 3
XTAL1 Input High Voltage VINH 2.5 V VDD = 3 V 3
Input Current -1 1 µA VIN = VDD 3
Input Current -70 µA VIN = GND; typically -40 µA at 5 V and -20 µA at 3 V 3
VOL, Output Low Voltage VOL 0.4 V VDD = 3 V, ISINK = 100 µA 3
VOH, Output High Voltage VOH 4 V VDD = 5 V, ISOURCE = 200 µA 3
Floating-State Leakage Current -10 10 µA 3
Power Supply Voltage (3 V) VDD, GND 2.7 3.6 V VDD = 3 V nom 3
Power Supply Voltage (5 V) VDD, GND 4.75 5.25 V VDD = 5 V nom 3
IDD Current (Normal Mode) IDD 1.5 mA VDD = 3 V 3
IDD Current (Normal Mode) IDD 1.7 mA VDD = 5 V 3
IDD (Power-Down Mode, CS = 1) IDD 9 µA VDD = 3 V 3
IDD (Power-Down Mode, CS = 1) IDD 24 µA VDD = 5 V 3
CH1/CH2 Select to CS Setup Time t2 0 ns 4
CS Falling Edge to DOUT Active t3 0 ns 4
CS Falling Edge to DOUT Active t3 60 ns VDD = 4.75 V to 5.25 V 4
CS Falling Edge to DOUT Active t3 80 ns VDD = 2.7 V to 3.6 V 4
SCLK Active Edge to Data Valid Delay t5 0 ns 4
SCLK Active Edge to Data Valid Delay t5 60 ns VDD = 4.75 V to 5.25 V 4
SCLK Active Edge to Data Valid Delay t5 80 ns VDD = 2.7 V to 3.6 V 4
Bus Relinquish Time after CS Inactive Edge t8 10 ns 4
Bus Relinquish Time after CS Inactive Edge t8 80 ns 4
CS Rising Edge to SCLK Inactive Edge Hold Time t9 0 ns 4
SCLK Inactive to DOUT High t10 10 ns 4
SCLK Inactive to DOUT High t10 80 ns 4
SCLK High Pulsewidth (Slave Mode) t6 100 ns 4
SCLK Low Pulsewidth (Slave Mode) t7 100 ns 4
VDD to GND VDD -0.3 7 V 5
Total AIN/REFIN Current 30 mA Indefinite 5
Operating Temperature Range -40 85 °C 5
Storage Temperature Range -65 150 °C 5
Junction Temperature 150 °C 5
Lead Temperature, Vapor Phase 215 °C 60 sec 5
Lead Temperature, Infrared 220 °C 15 sec 5
TSSOP θJC Thermal Impedance θJC 14 °C/W TSSOP Package 5

CAD (KiCad official)

  • Symbol: AD7782BRUZ
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: ad7782bruz-etched.step / ad7782bruz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7782bruz.step / ad7782bruz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (12 pp, sha256 0738d9e5e0c618b2, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF