# AD7780BRZ

**Analog Devices** · Analog To Digital Converters (ADCs) · SOIC-14

AD7780BRZ from Analog Devices, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCLK | input | Serial clock input for data transfers from the ADC, with a Schmitt-triggered input, and it can be active only when transferring data from the AD7780. |
| 2 | DOUT/RDY | tri_state | Dual-purpose pin that goes low to indicate a conversion is complete and serves as the serial data output, with its falling edge usable as a processor interrupt; it is tristated when PDRST is low. |
| 3 | NC | unconnected | No connect pin that can be left floating. |
| 4 | GAIN | input | Gain select pin: when low the gain is set to 128, and when high the gain is set to 1. |
| 5 | AIN(+) | input | Positive terminal of the differential analog input pair AIN(+)/AIN(−). |
| 6 | AIN(-) | input | Negative terminal of the differential analog input pair AIN(+)/AIN(−). |
| 7 | REFIN(+) | input | Positive reference input; the nominal reference REFIN(+) − REFIN(−) is 5 V, and the part can operate with a reference from 0.5 V to AVDD. |
| 8 | REFIN(-) | input | Negative reference input for the external reference applied between REFIN(+) and REFIN(−). |
| 9 | BPDSW | passive | Bridge power-down switch to GND, closed when PDRST is high and opened when PDRST is low. |
| 10 | GND | power_in | Ground reference point for the device. |
| 11 | AVDD | power_in | Analog supply voltage, 2.7 V to 5.25 V. |
| 12 | DVDD | power_in | Digital interface supply voltage, 2.7 V to 5.25 V, independent of AVDD, which sets the logic levels for the serial interface and digital control pins. |
| 13 | PDRST | input | Power-down/reset pin: when low the ADC is powered down, the low-side switch opens, logic is reset and DOUT/RDY is tristated; when high the ADC resumes conversion after the internal clock powers up in about 1 ms. |
| 14 | FILTER | input | Filter select pin: when low the 16.7 Hz fast-settling filter is selected (120 ms settling), and when high the 10 Hz high-rejection filter is selected (300 ms settling). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-14 |
| Category | Data Converters |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| AVDD to GND supply voltage | AVDD | 2.7 |  | 5.25 | V | AVDD to GND | 4 |
| DVDD to GND supply voltage | DVDD | 2.7 |  | 5.25 | V | DVDD to GND | 4 |
| Integral nonlinearity |  | -6 |  | 6 | ppm of FSR |  | 3 |
| Offset error |  | -6 |  | 6 | μV | Gain = 128 with FILTER = 1 | 3 |
| Offset error |  | -200 |  | 200 | μV | Gain = 1 with FILTER = 1 | 3 |
| Offset error |  | -1 |  | 1 | μV | Gain = 128 with FILTER = 0 | 3 |
| Offset error |  | -2 |  | 2 | μV | Gain = 1 with FILTER = 0 | 3 |
| Offset error drift vs. temperature |  | -10 |  | 10 | nV/°C | Gain = 128 | 3 |
| Offset error drift vs. temperature |  | -150 |  | 150 | nV/°C | Gain = 1 with FILTER = 1 | 3 |
| Full-scale error |  | -0.25 |  | 0.25 | % of FS |  | 3 |
| Gain drift vs. temperature |  | -2 |  | 2 | ppm/°C |  | 3 |
| Normal-mode rejection, 50 Hz, 60 Hz |  | 63 | 75 |  | dB | 50 Hz ± 1 Hz, 60 Hz ± 1 Hz, fADC = 16.7 Hz | 3 |
| Normal-mode rejection, 50 Hz, 60 Hz |  | 72 | 90 |  | dB | 50 Hz ± 1 Hz, 60 Hz ± 1 Hz, fADC = 10 Hz | 3 |
| Average input current |  | -1 |  | 1 | nA | Gain = 1 | 3 |
| Average input current drift |  | -3 |  | 3 | pA/°C |  | 3 |
| Reference voltage range |  | 0.5 |  |  | V | Lower limit 0.5 V; upper limit printed as AVDD | 3 |
| Absolute REFIN voltage limit |  | -30 |  |  | mV | Lower limit GND − 30 mV; upper limit printed as AVDD + 30 mV | 3 |
| Average reference input current drift |  | -0.15 |  | 0.15 | nA/V/°C |  | 3 |
| Bridge power-down switch on resistance | RON |  |  | 9 | Ω | BPDSW controlled via PDRST pin | 3 |
| Allowable current (bridge power-down switch) |  |  |  | 30 | mA | Continuous current | 3 |
| Internal clock frequency tolerance |  | -3 |  | 3 | % | Nominal 64 kHz | 3 |
| Input low voltage (SCLK, FILTER, GAIN, PDRST) | VINL |  |  | 0.4 | V | DVDD = 3 V | 4 |
| Input low voltage (SCLK, FILTER, GAIN, PDRST) | VINL |  |  | 0.8 | V | DVDD = 5 V | 4 |
| Input high voltage (SCLK, FILTER, GAIN, PDRST) | VINH | 1.8 |  |  | V | DVDD = 3 V | 4 |
| Input high voltage (SCLK, FILTER, GAIN, PDRST) | VINH | 2.4 |  |  | V | DVDD = 5 V | 4 |
| Input currents |  | -2 |  | 2 | μA | VIN = DVDD or GND | 4 |
| Output high voltage (DOUT/RDY) | VOH | 4 |  |  | V | DVDD = 5 V, ISOURCE = 200 μA | 4 |
| Output low voltage (DOUT/RDY) | VOL |  |  | 0.4 | V | DVDD = 3 V, ISINK = 100 μA | 4 |
| Floating-state leakage current |  | -2 |  | 2 | μA |  | 4 |
| SCLK high pulse width | t1 | 100 |  |  | ns |  | 5 |
| SCLK low pulse width | t2 | 100 |  |  | ns |  | 5 |
| SCLK active edge to data valid delay | t3 | 0 |  | 60 | ns | DVDD = 4.75 V to 5.25 V | 5 |
| SCLK active edge to data valid delay | t3 | 0 |  | 80 | ns | DVDD = 2.7 V to 3.6 V | 5 |
| SCLK inactive edge to DOUT/RDY high | t4 | 10 |  | 130 | ns |  | 5 |
| PDRST low pulse width | t5 | 100 |  |  | ns |  | 5 |
| IDD current, gain = 1 | IDD |  | 130 | 160 | μA | Gain = 1, AVDD = 5 V | 4 |
| IDD current, gain = 128 | IDD |  | 420 | 500 | μA | Gain = 128, AVDD = 5 V | 4 |
| Operating temperature range |  | -40 |  | 105 | °C |  | 6 |
| AVDD to GND |  | -0.3 |  | 7 | V |  | 6 |
| DVDD to GND |  | -0.3 |  | 7 | V |  | 6 |
| Analog input voltage to GND |  | -0.3 |  |  | V | Upper limit printed as AVDD + 0.3 V | 6 |
| Reference input voltage to GND |  | -0.3 |  |  | V | Upper limit printed as AVDD + 0.3 V | 6 |
| Digital input voltage to GND |  | -0.3 |  |  | V | Upper limit printed as DVDD + 0.3 V | 6 |
| Digital output voltage to GND |  | -0.3 |  |  | V | Upper limit printed as DVDD + 0.3 V | 6 |
| AIN/digital input current |  |  |  | 10 | mA |  | 6 |
| Storage temperature range |  | -65 |  | 150 | °C |  | 6 |
| Maximum junction temperature |  |  |  | 150 | °C |  | 6 |
| Lead temperature, soldering reflow |  |  |  | 260 | °C |  | 6 |
| Thermal resistance, junction-to-ambient, 14-lead SOIC | θJA |  | 104.5 |  | °C/W | Surface-mount, soldered in circuit board | 6 |
| Thermal resistance, junction-to-case, 14-lead SOIC | θJC |  | 42.9 |  | °C/W |  | 6 |

## CAD (KiCad official)

- Symbol: `AD7780BRZ`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `ad7780brz-etched.step` / `ad7780brz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7780brz.step` / `ad7780brz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7780.pdf) (16 pp, sha256 `963b0335a398a277`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad7780brz-datasheet.pdf)