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AD7771BCPZ

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Analog Devices Analog To Digital Converters (ADCs), LFCSP-64(9x9). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

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AD7771BCPZ

Analog Devices · Analog To Digital Converters (ADCs) · LFCSP-64(9x9)

AD7771BCPZ from Analog Devices, in a LFCSP-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AIN0− input Analog Input Channel 0, Negative, accepts differential or single-ended signals.
2 AIN0+ input Analog Input Channel 0, Positive, accepts differential or single-ended signals.
3 AIN1− input Analog Input Channel 1, Negative, accepts differential or single-ended signals.
4 AIN1+ input Analog Input Channel 1, Positive, accepts differential or single-ended signals.
5 AVSS1A power_in Negative Front-End Analog Supply for Channels 0-3, typical −1.65 V dual supply or AGND single supply; connect all AVSSx pins to same potential.
6 AVDD1A power_in Positive Front-End Analog Supply for Channels 0-3, typical AVSSx + 3.3 V; connect to AVDD1B.
7 REF1− input Negative Reference Input 1 for Channels 0-3, typical AVSSx; connect all REFx− pins to same potential.
8 REF1+ input Positive Reference Input 1 for Channels 0-3, typical REF1− + 2.5 V.
9 AIN2− input Analog Input Channel 2, Negative, accepts differential or single-ended signals.
10 AIN2+ input Analog Input Channel 2, Positive, accepts differential or single-ended signals.
11 AIN3− input Analog Input Channel 3, Negative, accepts differential or single-ended signals.
12 AIN3+ input Analog Input Channel 3, Positive, accepts differential or single-ended signals.
13 MODE0/GPIO0 bidirectional Mode 0 input in Pin Control Mode; configurable General-Purpose Input/Output 0 in SPI Control Mode; if unused, connect to DGND or IOVDD.
14 MODE1/GPIO1 bidirectional Mode 1 input in Pin Control Mode; configurable General-Purpose Input/Output 1 in SPI Control Mode; if unused, connect to DGND or IOVDD.
15 MODE2/GPIO2 bidirectional Mode 2 input in Pin Control Mode; configurable General-Purpose Input/Output 2 in SPI Control Mode; if unused, connect to DGND or IOVDD.
16 MODE3/ALERT bidirectional Mode 3 input in Pin Control Mode; Alert Output in SPI Control Mode.
17 CONVST_SAR input Σ-Δ Output Interface Selection Pin in Pin Control Mode; SAR ADC conversion start trigger in SPI Control Mode.
18 ALERT/CS bidirectional Alert Output in Pin Control Mode; Chip Select input in SPI Control Mode.
19 DCLK2/SCLK input Data Clock Frequency Selection Pin 2 in Pin Control Mode; SPI Clock in SPI Control Mode.
20 DCLK1/SDI input Data Clock Frequency Selection Pin 1 in Pin Control Mode; SPI Data Input in SPI Control Mode.
21 DCLK0/SDO output Data Clock Frequency Selection Pin 0 in Pin Control Mode; SPI Data Output in SPI Control Mode.
22 DGND power_in Digital Ground.
23 DREGCAP power_out Digital LDO Output; decouple this pin to DGND with 1 µF capacitor.
24 IOVDD power_in Digital I/O Supply and Digital LDO Supply from 1.8 V to 3.6 V; must not be lower than DREGCAP.
25 DOUT3 bidirectional Data Output Pin 3; acts as input pin in daisy-chain mode.
26 DOUT2 bidirectional Data Output Pin 2; acts as input pin in daisy-chain mode.
27 DOUT1 output Data Output Pin 1.
28 DOUT0 output Data Output Pin 0.
29 DCLK output Data Output Clock.
30 DRDY output Data Output Ready Pin.
31 XTAL1 input Crystal 1 Input Connection; tie to DGND if using CMOS clock source.
32 XTAL2/MCLK input Crystal 2 Input Connection or CMOS Master Clock input.
33 START input Synchronization Pulse input; internally synchronizes asynchronous pulse with MCLK; tie to DGND if unused.
34 SYNC_OUT output Synchronization Signal output generated by hardware via START pin or by software via SPI.
35 SYNC_IN input Reset for Internal Digital Block and Synchronization input for multiple devices.
36 RESET input Asynchronous Reset Pin; resets all registers to default value; pulse recommended after power-up.
37 AIN7+ input Analog Input Channel 7, Positive, accepts differential or single-ended signals.
38 AIN7− input Analog Input Channel 7, Negative, accepts differential or single-ended signals.
39 AIN6+ input Analog Input Channel 6, Positive, accepts differential or single-ended signals.
40 AIN6− input Analog Input Channel 6, Negative, accepts differential or single-ended signals.
41 REF2+ input Positive Reference Input 2 for Channels 4-7, typical REF2− + 2.5 V.
42 REF2− input Negative Reference Input 2 for Channels 4-7, typical AVSSx; connect all REFx− pins to same potential.
43 AVDD1B power_in Positive Front-End Analog Supply for Channels 4-7; connect to AVDD1A.
44 AVSS1B power_in Negative Front-End Analog Supply for Channels 4-7, typical −1.65 V dual supply or AGND single supply; connect all AVSSx pins to same potential.
45 AIN5+ input Analog Input Channel 5, Positive, accepts differential or single-ended signals.
46 AIN5− input Analog Input Channel 5, Negative, accepts differential or single-ended signals.
47 AIN4+ input Analog Input Channel 4, Positive, accepts differential or single-ended signals.
48 AIN4− input Analog Input Channel 4, Negative, accepts differential or single-ended signals.
49 REF_OUT output 2.5 V Reference Output; connect 100 nF capacitor if using internal reference.
50 AVSS2B power_in Negative Analog Supply; connect all AVSSx pins together.
51 AREG2CAP power_out Analog LDO Output 2; decouple to AVSS2B with 1 µF capacitor.
52 AVDD2B power_in Positive Analog Supply from 2.2 V to 3.6 V; connect to AVDD2A.
53 AVSS3 power_in Negative Analog Ground; connect all AVSSx to same potential.
54 FORMAT1 input Output Data Frame Configuration Pin 1 for DOUTx interface format selection.
55 FORMAT0 input Output Data Frame Configuration Pin 0 for DOUTx interface format selection.
56 CLK_SEL input Clock Source Selection pin; selects between CMOS clock input and crystal oscillator.
57 VCM output Common-Mode Voltage Output, typical (AVDD1x + AVSSx)/2, provides biased reference for input configurations.
58 AVDD2A power_in Positive Analog Supply from 2.2 V to 3.6 V; AVSS2x must not be lower than AREGxCAP; connect to AVDD2B.
59 AREG1CAP power_out Analog LDO Output 1; decouple to AVSSx with 1 µF capacitor.
60 AVSS2A power_in Negative Analog Supply; connect all AVSSx pins to same potential.
61 AVSS4 power_in Negative SAR Analog Supply and Reference; connect all AVSSx pins to same potential.
62 AVDD4 power_in Positive SAR Analog Supply and Reference Source from 3.0 V to 3.6 V.
63 AUXAIN+ input Positive SAR Analog Input Channel for on-chip diagnostics or external voltage measurement.
64 AUXAIN− input Negative SAR Analog Input Channel for on-chip diagnostics or external voltage measurement.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-64(9x9)
Category ADC/DAC/Data Conversion
Pins 65

CAD (KiCad official)

  • Symbol: AD7771BCPZ
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: LFCSP-64(9x9) (KiCad packages3D, STEP)
  • 3D model files: ad7771bcpz-etched.step / ad7771bcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7771bcpz.step / ad7771bcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (99 pp, sha256 4d717a37ccf61165, retrieved 2026-09-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF