component
AD7760BSVZ
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADCs), TQFP-64-EP(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.md+167ad7760bsvz-etched.glbad7760bsvz-hero.glbad7760bsvz-hero.overlay.json+1505ad7760bsvz.glbad7760bsvz.kicad_mod+655ad7760bsvz.kicad_sym+273ad7760bsvz.lbr+303ad7760bsvz.step+20284docs/ad7760bsvz-datasheet.pdfdocs/hero.pngpackage.json+537page.json+543viewers/footprint.html+1viewers/symbol.html+1README.mdadded+167@@ -0,0 +1,167 @@+# AD7760BSVZ++**Analog Devices** · Analog To Digital Converters (ADCs) · TQFP-64-EP(10x10)++AD7760BSVZ from Analog Devices, in a TQFP-64-EP(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | DGND | power_in | Ground reference for digital circuitry. |+| 2 | MCLKGND | power_in | Master clock ground sensing pin. |+| 3 | MCLK | input | Low jitter, buffered digital master clock input; the output data rate depends on this clock frequency. |+| 4 | AVDD2 | power_in | 5 V power supply, decoupled to AGND2 with 100 nF capacitors on pins 4, 14 and 15. |+| 5 | AGND2 | power_in | Analog ground for circuitry powered by AVDD2. |+| 6 | AVDD1 | power_in | 2.5 V power supply for the modulator, decoupled to AGND1 with 100 nF and 10 µF capacitors. |+| 7 | AGND1 | power_in | Analog ground for circuitry powered by AVDD1. |+| 8 | DECAPA | passive | Decoupling pin; a 100 nF capacitor must be connected between this pin and AGND. |+| 9 | REFGND | power_in | Reference ground, the ground connection for the reference voltage. |+| 10 | VREF+ | power_in | Reference input whose input range is set by the reference buffer supply AVDD4. |+| 11 | AGND4 | power_in | Analog ground for circuitry powered by AVDD4. |+| 12 | AVDD4 | power_in | 3.3 V to 5 V power supply for the reference buffer, decoupled to pin 9 with 10 nF in series with 10 Ω. |+| 13 | AGND2 | power_in | Analog ground for circuitry powered by AVDD2. |+| 14 | AVDD2 | power_in | 5 V power supply, decoupled to AGND2 with a 100 nF capacitor. |+| 15 | AVDD2 | power_in | 5 V power supply, decoupled to AGND2 with a 100 nF capacitor. |+| 16 | AGND2 | power_in | Analog ground for circuitry powered by AVDD2. |+| 17 | RBIAS | passive | Bias current setting pin; a resistor must be connected between this pin and AGND. |+| 18 | AGND2 | power_in | Analog ground for circuitry powered by AVDD2. |+| 19 | VINA+ | input | Positive input to the on-chip differential amplifier. |+| 20 | VINA- | input | Negative input to the on-chip differential amplifier. |+| 21 | VOUTA- | output | Negative output from the differential amplifier. |+| 22 | VOUTA+ | output | Positive output from the differential amplifier. |+| 23 | AGND3 | power_in | Analog ground for circuitry powered by AVDD3. |+| 24 | AVDD3 | power_in | 3.3 V to 5 V power supply for the differential amplifier, decoupled to AGND3 with 100 nF. |+| 25 | VIN+ | power_in | Positive fully differential input to the modulator. |+| 26 | VIN- | power_in | Negative fully differential input to the modulator. |+| 27 | AVDD2 | power_in | 5 V power supply; connected to pin 14 via a 15 nH inductor. |+| 28 | AGND2 | power_in | Analog ground for circuitry powered by AVDD2. |+| 29 | AGND3 | power_in | Analog ground for circuitry powered by AVDD3. |+| 30 | DECAPB | passive | Decoupling pin; a 33 pF capacitor must be connected between this pin and AGND3. |+| 31 | AGND3 | power_in | Analog ground for circuitry powered by AVDD3. |+| 32 | AGND3 | power_in | Analog ground for circuitry powered by AVDD3. |+| 33 | AVDD1 | power_in | 2.5 V power supply for the modulator, decoupled to AGND1 with 100 nF and 10 µF capacitors. |+| 34 | AGND1 | power_in | Analog ground for circuitry powered by AVDD1. |+| 35 | DGND | power_in | Ground reference for digital circuitry. |+| 36 | SYNC | input | Synchronization input; a falling edge resets the internal filter to synchronize multiple devices. |+| 37 | RESET | input | A falling edge resets all internal digital circuitry and powers down the part; holding it low keeps the device in reset. |+| 38 | DRDY | output | Data ready output that produces an active low pulse, ½ ICLK period wide, when new conversion data is available. |+| 39 | RD/WR | input | Read/write input; with CS low, a low level causes a read and a high level causes a write. |+| 40 | CS | input | Chip select input used with RD/WR to read and write data. |+| 41 | DVDD | power_in | 2.5 V power supply for digital circuitry and the FIR filter, decoupled to DGND with 100 nF. |+| 42 | DGND | power_in | Ground reference for digital circuitry. |+| 43 | DGND | power_in | Ground reference for digital circuitry. |+| 44 | VDRIVE | power_in | Logic power supply input, 1.8 V to 2.5 V, that sets the logic interface voltage; must be tied together with pin 63. |+| 45 | DB15 | bidirectional | 16-bit bidirectional data bus bit 15; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE. |+| 46 | DB14 | bidirectional | 16-bit bidirectional data bus bit 14; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE. |+| 47 | DB13 | bidirectional | 16-bit bidirectional data bus bit 13; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE. |+| 48 | DB12 | bidirectional | 16-bit bidirectional data bus bit 12; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE. |+| 49 | DB11 | bidirectional | 16-bit bidirectional data bus bit 11; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE. |+| 50 | DB10 | bidirectional | 16-bit bidirectional data bus bit 10; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE. |+| 51 | DB9 | bidirectional | 16-bit bidirectional data bus bit 9; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE. |+| 52 | DB8 | bidirectional | 16-bit bidirectional data bus bit 8; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE. |+| 53 | DGND | power_in | Ground reference for digital circuitry. |+| 54 | DB7 | bidirectional | 16-bit bidirectional data bus bit 7; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE. |+| 55 | DB6 | bidirectional | 16-bit bidirectional data bus bit 6; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE. |+| 56 | DB5 | bidirectional | 16-bit bidirectional data bus bit 5; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE. |+| 57 | DB4 | bidirectional | 16-bit bidirectional data bus bit 4; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE. |+| 58 | DB3 | bidirectional | 16-bit bidirectional data bus bit 3; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE. |+| 59 | DB2 | bidirectional | 16-bit bidirectional data bus bit 2; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE. |+| 60 | DB1 | bidirectional | 16-bit bidirectional data bus bit 1; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE. |+| 61 | DB0 | bidirectional | 16-bit bidirectional data bus bit 0; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE. |+| 62 | DGND | power_in | Ground reference for digital circuitry. |+| 63 | VDRIVE | power_in | Logic power supply input, 1.8 V to 2.5 V, that sets the logic interface voltage; must be tied together with pin 44. |+| 64 | DGND | power_in | Ground reference for digital circuitry. |+| 65 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | TQFP-64-EP(10x10) |+| Category | ADC/DAC/Data Conversion |+| Pins | 65 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Dynamic Range (decimate by 256) | | 119 | | | dB | Modulator inputs shorted | 4 |+| Dynamic Range (decimate by 32) | | 108 | | | dB | Modulator inputs shorted | 4 |+| Dynamic Range (decimate by 8) | | 99 | | | dB | Modulator inputs shorted | 4 |+| Zero Error | | | 0.014 | 0.02 | % | | 4 |+| VREF Input Voltage (VDD3 = 3.3 V ± 5%) | VREF | | | 2.5 | V | VDD3 = 3.3 V ± 5% | 5 |+| VREF Input Voltage (VDD3 = 5 V ± 5%) | VREF | | | 4.096 | V | VDD3 = 5 V ± 5% | 5 |+| VREF Input DC Leakage Current | | -6 | | 6 | µA | | 5 |+| VREF Input Capacitance | | | | 5 | pF | | 5 |+| Total Power Dissipation (normal mode) | | | | 958 | mW | Normal mode | 5 |+| Total Power Dissipation (low power mode) | | | | 661 | mW | Low power mode | 5 |+| Standby Mode Power Dissipation | | | | 6.35 | mW | Clock stopped | 5 |+| AVDD1 (Modulator Supply) tolerance | AVDD1 | -5 | | 5 | % | Nominal +2.5 V | 5 |+| AVDD2 (General Supply) tolerance | AVDD2 | -5 | | 5 | % | Nominal +5 V | 5 |+| DVDD tolerance | DVDD | -5 | | 5 | % | Nominal +2.5 V | 5 |+| AVDD3 (Differential Amplifier Supply) | AVDD3 | 3.15 | | 5.25 | V | | 5 |+| AVDD4 (Reference Buffer Supply) | AVDD4 | 3.15 | | 5.25 | V | | 5 |+| VDRIVE Logic Supply | VDRIVE | 1.65 | | 2.7 | V | | 5 |+| AIDD1 (Modulator), normal mode | AIDD1 | | 49 | 51 | mA | Normal mode | 5 |+| AIDD2 (General), normal mode | AIDD2 | | 40 | 42 | mA | Normal mode | 5 |+| AIDD4 (Reference Buffer), normal mode | AIDD4 | | 34 | 36 | mA | AVDD4 = 5 V, normal mode | 5 |+| AIDD1 (Modulator), low power mode | AIDD1 | | 26 | 28 | mA | Low power mode | 5 |+| AIDD2 (General), low power mode | AIDD2 | | 20 | 23 | mA | Low power mode | 5 |+| AIDD4 (Reference Buffer), low power mode | AIDD4 | | 9 | 10 | mA | AVDD4 = 5 V, low power mode | 5 |+| AIDD3 (Differential Amplifier) | AIDD3 | | 41 | 44 | mA | AVDD3 = 5 V, both modes | 5 |+| DIDD | DIDD | | 63 | 70 | mA | Both modes | 5 |+| Input Leakage Current | | -5 | | 5 | µA | | 5 |+| Three-State Leakage Current (D15:D0) | | -5 | | 5 | µA | | 5 |+| VINH Input High Voltage | VINH | 0.7 | | | V | × VDRIVE | 5 |+| VINL Input Low Voltage | VINL | | | 0.3 | V | × VDRIVE | 5 |+| VOH high-level output voltage | VOH5 | 1.5 | | | V | Tested using minimum VDRIVE of 1.65 V with 400 µA load current | 5 |+| VOL low-level output voltage | VOL4 | | | 0.1 | V | | 5 |+| Master clock frequency fMCLK | fMCLK | 1 | | 40 | MHz | Applied master clock frequency | 6 |+| DRDY falling edge to CS falling edge | t2 | 10 | | | ns | | 6 |+| RD/WR setup time to CS falling edge | t3 | 3 | | | ns | | 6 |+| Bus relinquish time | t8 | | | 11 | ns | | 6 |+| RD/WR hold time to CS rising edge | t7 | 3 | | | ns | | 6 |+| Data valid prior to DRDY rising edge | t12 | 23 | | | ns | Modulator output mode with CDIV = 1 | 6 |+| Data valid after DRDY rising edge | t13 | 19 | | | ns | Modulator output mode with CDIV = 1 | 6 |+| Bus relinquish time (write) | t14 | | | 11 | ns | | 6 |+| Data setup time | t17 | 5 | | | ns | | 6 |+| Data hold time | t18 | 0 | | | ns | | 6 |+| Data valid prior to MCLK falling edge while DRDY low | t19 | 23 | | | ns | Modulator output mode with CDIV = 0 | 6 |+| Data valid after MCLK falling edge while DRDY low | t20 | 19 | | | ns | Modulator output mode with CDIV = 0 | 6 |+| Voltage on any pin, AVDD1 to GND | AVDD1 | -0.3 | | 3 | V | to GND | 8 |+| Voltage on AVDD2:AVDD4 to GND | AVDD2:AVDD4 | -0.3 | | 6 | V | to GND | 8 |+| Voltage on DVDD to GND | DVDD | -0.3 | | 3 | V | to GND | 8 |+| Voltage on VDRIVE to GND | VDRIVE | -0.3 | | 3 | V | to GND | 8 |+| Voltage on VIN+, VIN− to GND | VIN+, VIN− | -0.3 | | 6 | V | to GND | 8 |+| Voltage on VINA+, VINA− to GND | VINA+, VINA− | -0.3 | | 6 | V | to GND | 8 |+| Voltage on MCLK to MCLKGND | MCLK | -0.3 | | 6 | V | to MCLKGND | 8 |+| AGND to DGND voltage | AGND | -0.3 | | 0.3 | V | to DGND | 8 |+| Input Current to Any Pin Except Supplies | | -10 | | 10 | mA | | 8 |+| Operating Temperature Range (commercial) | | -40 | | 85 | °C | Commercial | 8 |+| Storage Temperature Range | | -65 | | 150 | °C | | 8 |+| Junction Temperature | | | | 150 | °C | | 8 |+| Lead Temperature, Vapor Phase | | | | 215 | °C | 60 sec | 8 |+| Lead Temperature, Infrared | | | | 220 | °C | 15 sec | 8 |+| θJA Thermal Impedance (TQFP exposed paddle) | θJA | | 92.7 | | °C/W | | 8 |+| θJC Thermal Impedance (TQFP exposed paddle) | θJC | | 5.1 | | °C/W | | 8 |++## CAD (KiCad official)++- Symbol: `AD7760BSVZ`+- Footprint: `Package_QFP:TQFP-64-1EP_10x10mm_P0.5mm_EP5.305x5.305mm`+- 3D model: TQFP-64-EP(10x10) (KiCad packages3D, STEP)+- 3D model files: `ad7760bsvz-etched.step` / `ad7760bsvz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7760bsvz.step` / `ad7760bsvz.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7760.pdf) (36 pp, sha256 `b78a13723854dcd1`, retrieved 2026-10-30, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ad7760bsvz-datasheet.pdf)
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<pin name="AGND3@4" x="-17.78" y="-38.1" length="middle" direction="pwr"/>+ <pin name="AVDD1@2" x="-17.78" y="-40.64" length="middle" direction="pwr"/>+ <pin name="EP" x="17.78" y="38.1" length="middle" direction="pas" rot="R180"/>+ <pin name="DGND@2" x="17.78" y="35.56" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDRIVE" x="17.78" y="33.02" length="middle" direction="pwr" rot="R180"/>+ <pin name="DGND@3" x="17.78" y="30.48" length="middle" direction="pwr" rot="R180"/>+ <pin name="DB0" x="17.78" y="27.94" length="middle" direction="io" rot="R180"/>+ <pin name="DB1" x="17.78" y="25.4" length="middle" direction="io" rot="R180"/>+ <pin name="DB2" x="17.78" y="22.86" length="middle" direction="io" rot="R180"/>+ <pin name="DB3" x="17.78" y="20.32" length="middle" direction="io" rot="R180"/>+ <pin name="DB4" x="17.78" y="17.78" length="middle" direction="io" rot="R180"/>+ <pin name="DB5" x="17.78" y="15.24" length="middle" direction="io" rot="R180"/>+ <pin name="DB6" x="17.78" y="12.7" length="middle" direction="io" rot="R180"/>+ <pin name="DB7" x="17.78" y="10.16" length="middle" direction="io" rot="R180"/>+ <pin name="DGND@4" x="17.78" y="7.62" length="middle" direction="pwr" rot="R180"/>+ <pin name="DB8" x="17.78" y="5.08" length="middle" direction="io" rot="R180"/>+ <pin name="DB9" x="17.78" y="2.54" length="middle" direction="io" rot="R180"/>+ <pin name="DB10" x="17.78" y="0" length="middle" direction="io" rot="R180"/>+ <pin name="DB11" x="17.78" y="-2.54" length="middle" direction="io" rot="R180"/>+ <pin name="DB12" x="17.78" y="-5.08" length="middle" direction="io" rot="R180"/>+ <pin name="DB13" x="17.78" y="-7.62" length="middle" direction="io" rot="R180"/>+ <pin name="DB14" x="17.78" y="-10.16" length="middle" direction="io" rot="R180"/>+ <pin name="DB15" x="17.78" y="-12.7" length="middle" direction="io" rot="R180"/>+ <pin name="VDRIVE@2" x="17.78" y="-15.24" length="middle" direction="pwr" rot="R180"/>+ <pin name="DGND@5" x="17.78" y="-17.78" length="middle" direction="pwr" rot="R180"/>+ <pin name="DGND@6" x="17.78" y="-20.32" length="middle" direction="pwr" rot="R180"/>+ <pin name="DVDD" x="17.78" y="-22.86" length="middle" direction="pwr" rot="R180"/>+ <pin name="CS" x="17.78" y="-25.4" length="middle" direction="in" rot="R180"/>+ <pin name="RD/WR" x="17.78" y="-27.94" length="middle" direction="in" rot="R180"/>+ <pin name="DRDY" x="17.78" y="-30.48" length="middle" direction="out" rot="R180"/>+ <pin name="RESET" x="17.78" y="-33.02" length="middle" direction="in" rot="R180"/>+ <pin name="SYNC" x="17.78" y="-35.56" length="middle" direction="in" rot="R180"/>+ <pin name="DGND@7" x="17.78" y="-38.1" length="middle" direction="pwr" rot="R180"/>+ <pin name="AGND1@2" x="17.78" y="-40.64" length="middle" direction="pwr" rot="R180"/>+</symbol>+</symbols>+<devicesets>+<deviceset name="AD7760BSVZ" prefix="U">+ <description></description>+ <gates>+ <gate name="G$1" symbol="AD7760BSVZ" x="0" y="0"/>+ </gates>+ <devices>+ <device name="" package="TQFP-64-1EP_10x10mm_P0.5mm_EP5.305x5.305mm">+ <connects>+ <connect gate="G$1" pin="DGND" pad="1"/>+ <connect gate="G$1" pin="MCLKGND" pad="2"/>+ <connect gate="G$1" pin="MCLK" pad="3"/>+ <connect gate="G$1" pin="AVDD2" pad="4"/>+ <connect gate="G$1" pin="AGND2" pad="5"/>+ <connect gate="G$1" pin="AVDD1" pad="6"/>+ <connect gate="G$1" pin="AGND1" pad="7"/>+ <connect gate="G$1" pin="DECAPA" pad="8"/>+ <connect gate="G$1" pin="REFGND" pad="9"/>+ <connect gate="G$1" pin="VREF+" pad="10"/>+ <connect gate="G$1" pin="AGND4" pad="11"/>+ <connect gate="G$1" pin="AVDD4" pad="12"/>+ <connect gate="G$1" pin="AGND2@2" pad="13"/>+ <connect gate="G$1" pin="AVDD2@2" pad="14"/>+ <connect gate="G$1" pin="AVDD2@3" pad="15"/>+ <connect gate="G$1" pin="AGND2@3" pad="16"/>+ <connect gate="G$1" pin="RBIAS" pad="17"/>+ <connect gate="G$1" pin="AGND2@4" pad="18"/>+ <connect gate="G$1" pin="VINA+" pad="19"/>+ <connect gate="G$1" pin="VINA-" pad="20"/>+ <connect gate="G$1" pin="VOUTA-" pad="21"/>+ <connect gate="G$1" pin="VOUTA+" pad="22"/>+ <connect gate="G$1" pin="AGND3" pad="23"/>+ <connect gate="G$1" pin="AVDD3" pad="24"/>+ <connect gate="G$1" pin="VIN+" pad="25"/>+ <connect gate="G$1" pin="VIN-" pad="26"/>+ <connect gate="G$1" pin="AVDD2@4" pad="27"/>+ <connect gate="G$1" pin="AGND2@5" pad="28"/>+ <connect gate="G$1" pin="AGND3@2" pad="29"/>+ <connect gate="G$1" pin="DECAPB" pad="30"/>+ <connect gate="G$1" pin="AGND3@3" pad="31"/>+ <connect gate="G$1" pin="AGND3@4" pad="32"/>+ <connect gate="G$1" pin="AVDD1@2" pad="33"/>+ <connect gate="G$1" pin="EP" pad="65"/>+ <connect gate="G$1" pin="DGND@2" pad="64"/>+ <connect gate="G$1" pin="VDRIVE" pad="63"/>+ <connect gate="G$1" pin="DGND@3" pad="62"/>+ <connect gate="G$1" pin="DB0" pad="61"/>+ <connect gate="G$1" pin="DB1" pad="60"/>+ <connect gate="G$1" pin="DB2" pad="59"/>+ <connect gate="G$1" pin="DB3" pad="58"/>+ <connect gate="G$1" pin="DB4" pad="57"/>+ <connect gate="G$1" pin="DB5" pad="56"/>+ <connect gate="G$1" pin="DB6" pad="55"/>+ <connect gate="G$1" pin="DB7" pad="54"/>+ <connect gate="G$1" pin="DGND@4" pad="53"/>+ <connect gate="G$1" pin="DB8" pad="52"/>+ <connect gate="G$1" pin="DB9" pad="51"/>+ <connect gate="G$1" pin="DB10" pad="50"/>+ <connect gate="G$1" pin="DB11" pad="49"/>+ <connect gate="G$1" pin="DB12" pad="48"/>+ <connect gate="G$1" pin="DB13" pad="47"/>+ <connect gate="G$1" pin="DB14" pad="46"/>+ <connect gate="G$1" pin="DB15" pad="45"/>+ <connect gate="G$1" pin="VDRIVE@2" pad="44"/>+ <connect gate="G$1" pin="DGND@5" pad="43"/>+ <connect gate="G$1" pin="DGND@6" pad="42"/>+ <connect gate="G$1" pin="DVDD" pad="41"/>+ <connect gate="G$1" pin="CS" pad="40"/>+ <connect gate="G$1" pin="RD/WR" pad="39"/>+ <connect gate="G$1" pin="DRDY" pad="38"/>+ <connect gate="G$1" pin="RESET" pad="37"/>+ <connect gate="G$1" pin="SYNC" pad="36"/>+ <connect gate="G$1" pin="DGND@7" pad="35"/>+ <connect gate="G$1" pin="AGND1@2" pad="34"/>+ </connects>+ <technologies><technology name=""/></technologies>+ </device>+ </devices>+</deviceset>+</devicesets>+</library>+</drawing>+</eagle>
ad7760bsvz.stepadded+20284@@ -0,0 +1,20284 @@+ISO-10303-21;+HEADER;+/* TQFP-64-1EP_10x10mm_P0.5mm_EP5.305x5.305mm.step 3D STEP model for use in ECAD systems+ * Copyright (C) 2025, KiCAD+ *+ * This work is licensed under the+ * [Creative Commons CC-BY-SA 4.0 License](https://creativecommons.org/licenses/by-sa/4.0/legalcode),+ * with the following exception:+ *+ * To the extent that the creation of electronic designs that use 'Licensed Material' can be+ * considered to be 'Adapted Material', then the copyright holder waives article 3 of the license+ * with respect to these designs and any generated files which use data provided as part of the+ * 'Licensed Material'.+ *+ * You are free to use the library data in your own projects without the obligation to share your+ * project files under this or any other license agreement. However, if you wish to distribute+ * these libraries, or parts thereof (including in modified form) as a collection then the exception+ * above does not apply. Please refer to+ * https://gitlab.com/kicad/libraries/kicad-packages3D/-/blob/master/LICENSE.md for further clarification+ * of the exception.+ *+ * Disclaimer of Warranties and Limitation of Liability.+ * These libraries are provided in the hope that they will be useful, but are provided without warranty of any kind, express or implied.+ * USE 3D CAD DATA AT YOUR OWN RISK+ * DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.+ */++FILE_DESCRIPTION(+/* description */ ('model of TQFP-64-1EP_10x10mm_P0.5mm_EP5.305x5.305mm'),+/* implementation_level */ '2;1');++FILE_NAME(+/* name */ 'TQFP-64-1EP_10x10mm_P0.5mm_EP5.305x5.305mm.step',+/* time_stamp */ '1970-01-01T00:00:00',+/* author */ ('KiCAD','kicad'),+/* organization */ ('OCCT'),+/* preprocessor_version */ '',+/* originating_system */ 'KiCAD',+/* authorisation */ '');++FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));+ENDSEC;++DATA;+#1=APPLICATION_PROTOCOL_DEFINITION('international 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BOUNDED_SURFACE() B_SPLINE_SURFACE(2,2,((#33,#34,#35,#36,#37),(#254,#255,#256,#257,#258),(#231,#232,#233,#234,#235)),.UNSPECIFIED.,.F.,.F.,.F.) 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B_SPLINE_SURFACE_WITH_KNOTS((3,3),(3,1,1,3),(0.,0.843180249799),(-0.220853681277,-3.998243283511E-02,0.803197816964,0.984069065406),.UNSPECIFIED.) GEOMETRIC_REPRESENTATION_ITEM() RATIONAL_B_SPLINE_SURFACE(((1.,1.,1.,1.,1.),(0.781002645201,0.781002645201,0.781002645201,0.781002645201,0.781002645201),(1.,1.,1.,1.,1.))) REPRESENTATION_ITEM('') SURFACE() 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B_SPLINE_SURFACE_WITH_KNOTS((3,3),(3,1,1,3),(0.,0.843180249799),(-0.220853681277,-3.998243283511E-02,0.803197816964,0.984069065406),.UNSPECIFIED.) GEOMETRIC_REPRESENTATION_ITEM() RATIONAL_B_SPLINE_SURFACE(((1.,1.,1.,1.,1.),(0.781002645201,0.781002645201,0.781002645201,0.781002645201,0.781002645201),(1.,1.,1.,1.,1.))) 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B_SPLINE_SURFACE_WITH_KNOTS((3,3),(3,1,1,3),(0.,0.843180249799),(-0.220853681277,-3.998243283511E-02,0.803197816964,0.984069065406),.UNSPECIFIED.) GEOMETRIC_REPRESENTATION_ITEM() RATIONAL_B_SPLINE_SURFACE(((1.,1.,1.,1.,1.),(0.781002645201,0.781002645201,0.781002645201,0.781002645201,0.781002645201),(1.,1.,1.,1.,1.))) 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B_SPLINE_SURFACE_WITH_KNOTS((3,3),(3,1,1,3),(0.,8.660327950568),(-0.460534155493,-4.048920165975E-02,8.619838748908,9.039883702742),.UNSPECIFIED.) GEOMETRIC_REPRESENTATION_ITEM() RATIONAL_B_SPLINE_SURFACE(((1.,1.,1.,1.,1.),(0.777145961457,0.777145961457,0.777145961457,0.777145961457,0.777145961457),(1.,1.,1.,1.,1.))) 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package.jsonadded+537@@ -0,0 +1,537 @@+{+ "slug": "ad7760bsvz",+ "version": "0.1.0",+ "type": "component",+ "description": "Analog Devices Analog To Digital Converters (ADCs), TQFP-64-EP(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "adc-dac-data conversion",+ "ad7760bsvz",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ad7760bsvz.kicad_sym",+ "ad7760bsvz.kicad_mod",+ "ad7760bsvz.glb",+ "ad7760bsvz.step",+ "ad7760bsvz.lbr",+ "docs/hero.png",+ "docs/ad7760bsvz-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "ad7760bsvz-hero.glb",+ "ad7760bsvz-hero.overlay.json",+ "ad7760bsvz-etched.glb"+ ],+ "component": {+ "mpn": "AD7760BSVZ",+ "manufacturer": "Analog Devices",+ "package": "TQFP-64-EP(10x10)",+ "pin_count": 65,+ "category": "ADC/DAC/Data Conversion",+ "subcategory": "Analog To Digital Converters (ADCs)",+ "datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD7760.pdf",+ "parts": {+ "symbol": "ad7760bsvz.kicad_sym",+ "footprint": "ad7760bsvz.kicad_mod",+ "model_3d": "ad7760bsvz-hero.glb",+ "model_3d_plain": "ad7760bsvz-etched.glb",+ "model_3d_step": "ad7760bsvz-etched.step",+ "model_3d_step_plain": "ad7760bsvz.step",+ "lbr": "ad7760bsvz.lbr"+ },+ "distributor_links": {+ "lcsc": "C578509",+ "digikey": "505-AD7760BSVZ-ND",+ "mouser": "584-AD7760BSVZ"+ },+ "distributor_check": {+ "checked_at": "2026-10-30T22:45:52Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "505-AD7760BSVZ-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "584-AD7760BSVZ",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "DGND",+ "type": "power_in",+ "description": "Ground reference for digital circuitry."+ },+ {+ "number": "2",+ "name": "MCLKGND",+ "type": "power_in",+ "description": "Master clock ground sensing pin."+ },+ {+ "number": "3",+ "name": "MCLK",+ "type": "input",+ "description": "Low jitter, buffered digital master clock input; the output data rate depends on this clock frequency."+ },+ {+ "number": "4",+ "name": "AVDD2",+ "type": "power_in",+ "description": "5 V power supply, decoupled to AGND2 with 100 nF capacitors on pins 4, 14 and 15."+ },+ {+ "number": "5",+ "name": "AGND2",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD2."+ },+ {+ "number": "6",+ "name": "AVDD1",+ "type": "power_in",+ "description": "2.5 V power supply for the modulator, decoupled to AGND1 with 100 nF and 10 µF capacitors."+ },+ {+ "number": "7",+ "name": "AGND1",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD1."+ },+ {+ "number": "8",+ "name": "DECAPA",+ "type": "passive",+ "description": "Decoupling pin; a 100 nF capacitor must be connected between this pin and AGND."+ },+ {+ "number": "9",+ "name": "REFGND",+ "type": "power_in",+ "description": "Reference ground, the ground connection for the reference voltage."+ },+ {+ "number": "10",+ "name": "VREF+",+ "type": "power_in",+ "description": "Reference input whose input range is set by the reference buffer supply AVDD4."+ },+ {+ "number": "11",+ "name": "AGND4",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD4."+ },+ {+ "number": "12",+ "name": "AVDD4",+ "type": "power_in",+ "description": "3.3 V to 5 V power supply for the reference buffer, decoupled to pin 9 with 10 nF in series with 10 Ω."+ },+ {+ "number": "13",+ "name": "AGND2",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD2."+ },+ {+ "number": "14",+ "name": "AVDD2",+ "type": "power_in",+ "description": "5 V power supply, decoupled to AGND2 with a 100 nF capacitor."+ },+ {+ "number": "15",+ "name": "AVDD2",+ "type": "power_in",+ "description": "5 V power supply, decoupled to AGND2 with a 100 nF capacitor."+ },+ {+ "number": "16",+ "name": "AGND2",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD2."+ },+ {+ "number": "17",+ "name": "RBIAS",+ "type": "passive",+ "description": "Bias current setting pin; a resistor must be connected between this pin and AGND."+ },+ {+ "number": "18",+ "name": "AGND2",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD2."+ },+ {+ "number": "19",+ "name": "VINA+",+ "type": "input",+ "description": "Positive input to the on-chip differential amplifier."+ },+ {+ "number": "20",+ "name": "VINA-",+ "type": "input",+ "description": "Negative input to the on-chip differential amplifier."+ },+ {+ "number": "21",+ "name": "VOUTA-",+ "type": "output",+ "description": "Negative output from the differential amplifier."+ },+ {+ "number": "22",+ "name": "VOUTA+",+ "type": "output",+ "description": "Positive output from the differential amplifier."+ },+ {+ "number": "23",+ "name": "AGND3",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD3."+ },+ {+ "number": "24",+ "name": "AVDD3",+ "type": "power_in",+ "description": "3.3 V to 5 V power supply for the differential amplifier, decoupled to AGND3 with 100 nF."+ },+ {+ "number": "25",+ "name": "VIN+",+ "type": "power_in",+ "description": "Positive fully differential input to the modulator."+ },+ {+ "number": "26",+ "name": "VIN-",+ "type": "power_in",+ "description": "Negative fully differential input to the modulator."+ },+ {+ "number": "27",+ "name": "AVDD2",+ "type": "power_in",+ "description": "5 V power supply; connected to pin 14 via a 15 nH inductor."+ },+ {+ "number": "28",+ "name": "AGND2",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD2."+ },+ {+ "number": "29",+ "name": "AGND3",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD3."+ },+ {+ "number": "30",+ "name": "DECAPB",+ "type": "passive",+ "description": "Decoupling pin; a 33 pF capacitor must be connected between this pin and AGND3."+ },+ {+ "number": "31",+ "name": "AGND3",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD3."+ },+ {+ "number": "32",+ "name": "AGND3",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD3."+ },+ {+ "number": "33",+ "name": "AVDD1",+ "type": "power_in",+ "description": "2.5 V power supply for the modulator, decoupled to AGND1 with 100 nF and 10 µF capacitors."+ },+ {+ "number": "34",+ "name": "AGND1",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD1."+ },+ {+ "number": "35",+ "name": "DGND",+ "type": "power_in",+ "description": "Ground reference for digital circuitry."+ },+ {+ "number": "36",+ "name": "SYNC",+ "type": "input",+ "description": "Synchronization input; a falling edge resets the internal filter to synchronize multiple devices."+ },+ {+ "number": "37",+ "name": "RESET",+ "type": "input",+ "description": "A falling edge resets all internal digital circuitry and powers down the part; holding it low keeps the device in reset."+ },+ {+ "number": "38",+ "name": "DRDY",+ "type": "output",+ "description": "Data ready output that produces an active low pulse, ½ ICLK period wide, when new conversion data is available."+ },+ {+ "number": "39",+ "name": "RD/WR",+ "type": "input",+ "description": "Read/write input; with CS low, a low level causes a read and a high level causes a write."+ },+ {+ "number": "40",+ "name": "CS",+ "type": "input",+ "description": "Chip select input used with RD/WR to read and write data."+ },+ {+ "number": "41",+ "name": "DVDD",+ "type": "power_in",+ "description": "2.5 V power supply for digital circuitry and the FIR filter, decoupled to DGND with 100 nF."+ },+ {+ "number": "42",+ "name": "DGND",+ "type": "power_in",+ "description": "Ground reference for digital circuitry."+ },+ {+ "number": "43",+ "name": "DGND",+ "type": "power_in",+ "description": "Ground reference for digital circuitry."+ },+ {+ "number": "44",+ "name": "VDRIVE",+ "type": "power_in",+ "description": "Logic power supply input, 1.8 V to 2.5 V, that sets the logic interface voltage; must be tied together with pin 63."+ },+ {+ "number": "45",+ "name": "DB15",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 15; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "46",+ "name": "DB14",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 14; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "47",+ "name": "DB13",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 13; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "48",+ "name": "DB12",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 12; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "49",+ "name": "DB11",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 11; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "50",+ "name": "DB10",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 10; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "51",+ "name": "DB9",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 9; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "52",+ "name": "DB8",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 8; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "53",+ "name": "DGND",+ "type": "power_in",+ "description": "Ground reference for digital circuitry."+ },+ {+ "number": "54",+ "name": "DB7",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 7; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "55",+ "name": "DB6",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 6; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "56",+ "name": "DB5",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 5; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "57",+ "name": "DB4",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 4; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "58",+ "name": "DB3",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 3; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "59",+ "name": "DB2",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 2; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "60",+ "name": "DB1",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 1; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "61",+ "name": "DB0",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 0; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "62",+ "name": "DGND",+ "type": "power_in",+ "description": "Ground reference for digital circuitry."+ },+ {+ "number": "63",+ "name": "VDRIVE",+ "type": "power_in",+ "description": "Logic power supply input, 1.8 V to 2.5 V, that sets the logic interface voltage; must be tied together with pin 44."+ },+ {+ "number": "64",+ "name": "DGND",+ "type": "power_in",+ "description": "Ground reference for digital circuitry."+ },+ {+ "number": "65",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pinout taken from the 64-lead TQFP_EP entries in Table 5 and the pin list on pages 9-10; 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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "adc-dac-data conversion",+ "ad7760bsvz",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "ad7760bsvz.kicad_sym",+ "ad7760bsvz.kicad_mod",+ "ad7760bsvz.glb",+ "ad7760bsvz.step",+ "ad7760bsvz.lbr",+ "docs/hero.png",+ "docs/ad7760bsvz-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "ad7760bsvz-hero.glb",+ "ad7760bsvz-hero.overlay.json",+ "ad7760bsvz-etched.glb"+ ],+ "component": {+ "mpn": "AD7760BSVZ",+ "manufacturer": "Analog Devices",+ "package": "TQFP-64-EP(10x10)",+ "pin_count": 65,+ "category": "ADC/DAC/Data Conversion",+ "subcategory": "Analog To Digital Converters (ADCs)",+ "datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD7760.pdf",+ "parts": {+ "symbol": "ad7760bsvz.kicad_sym",+ "footprint": "ad7760bsvz.kicad_mod",+ "model_3d": "ad7760bsvz-hero.glb",+ "model_3d_plain": "ad7760bsvz-etched.glb",+ "model_3d_step": "ad7760bsvz-etched.step",+ "model_3d_step_plain": "ad7760bsvz.step",+ "lbr": "ad7760bsvz.lbr"+ },+ "distributor_links": {+ "lcsc": "C578509",+ "digikey": "505-AD7760BSVZ-ND",+ "mouser": "584-AD7760BSVZ"+ },+ "distributor_check": {+ "checked_at": "2026-10-30T22:45:52Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "505-AD7760BSVZ-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "584-AD7760BSVZ",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "DGND",+ "type": "power_in",+ "description": "Ground reference for digital circuitry."+ },+ {+ "number": "2",+ "name": "MCLKGND",+ "type": "power_in",+ "description": "Master clock ground sensing pin."+ },+ {+ "number": "3",+ "name": "MCLK",+ "type": "input",+ "description": "Low jitter, buffered digital master clock input; the output data rate depends on this clock frequency."+ },+ {+ "number": "4",+ "name": "AVDD2",+ "type": "power_in",+ "description": "5 V power supply, decoupled to AGND2 with 100 nF capacitors on pins 4, 14 and 15."+ },+ {+ "number": "5",+ "name": "AGND2",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD2."+ },+ {+ "number": "6",+ "name": "AVDD1",+ "type": "power_in",+ "description": "2.5 V power supply for the modulator, decoupled to AGND1 with 100 nF and 10 µF capacitors."+ },+ {+ "number": "7",+ "name": "AGND1",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD1."+ },+ {+ "number": "8",+ "name": "DECAPA",+ "type": "passive",+ "description": "Decoupling pin; a 100 nF capacitor must be connected between this pin and AGND."+ },+ {+ "number": "9",+ "name": "REFGND",+ "type": "power_in",+ "description": "Reference ground, the ground connection for the reference voltage."+ },+ {+ "number": "10",+ "name": "VREF+",+ "type": "power_in",+ "description": "Reference input whose input range is set by the reference buffer supply AVDD4."+ },+ {+ "number": "11",+ "name": "AGND4",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD4."+ },+ {+ "number": "12",+ "name": "AVDD4",+ "type": "power_in",+ "description": "3.3 V to 5 V power supply for the reference buffer, decoupled to pin 9 with 10 nF in series with 10 Ω."+ },+ {+ "number": "13",+ "name": "AGND2",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD2."+ },+ {+ "number": "14",+ "name": "AVDD2",+ "type": "power_in",+ "description": "5 V power supply, decoupled to AGND2 with a 100 nF capacitor."+ },+ {+ "number": "15",+ "name": "AVDD2",+ "type": "power_in",+ "description": "5 V power supply, decoupled to AGND2 with a 100 nF capacitor."+ },+ {+ "number": "16",+ "name": "AGND2",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD2."+ },+ {+ "number": "17",+ "name": "RBIAS",+ "type": "passive",+ "description": "Bias current setting pin; a resistor must be connected between this pin and AGND."+ },+ {+ "number": "18",+ "name": "AGND2",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD2."+ },+ {+ "number": "19",+ "name": "VINA+",+ "type": "input",+ "description": "Positive input to the on-chip differential amplifier."+ },+ {+ "number": "20",+ "name": "VINA-",+ "type": "input",+ "description": "Negative input to the on-chip differential amplifier."+ },+ {+ "number": "21",+ "name": "VOUTA-",+ "type": "output",+ "description": "Negative output from the differential amplifier."+ },+ {+ "number": "22",+ "name": "VOUTA+",+ "type": "output",+ "description": "Positive output from the differential amplifier."+ },+ {+ "number": "23",+ "name": "AGND3",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD3."+ },+ {+ "number": "24",+ "name": "AVDD3",+ "type": "power_in",+ "description": "3.3 V to 5 V power supply for the differential amplifier, decoupled to AGND3 with 100 nF."+ },+ {+ "number": "25",+ "name": "VIN+",+ "type": "power_in",+ "description": "Positive fully differential input to the modulator."+ },+ {+ "number": "26",+ "name": "VIN-",+ "type": "power_in",+ "description": "Negative fully differential input to the modulator."+ },+ {+ "number": "27",+ "name": "AVDD2",+ "type": "power_in",+ "description": "5 V power supply; connected to pin 14 via a 15 nH inductor."+ },+ {+ "number": "28",+ "name": "AGND2",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD2."+ },+ {+ "number": "29",+ "name": "AGND3",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD3."+ },+ {+ "number": "30",+ "name": "DECAPB",+ "type": "passive",+ "description": "Decoupling pin; a 33 pF capacitor must be connected between this pin and AGND3."+ },+ {+ "number": "31",+ "name": "AGND3",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD3."+ },+ {+ "number": "32",+ "name": "AGND3",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD3."+ },+ {+ "number": "33",+ "name": "AVDD1",+ "type": "power_in",+ "description": "2.5 V power supply for the modulator, decoupled to AGND1 with 100 nF and 10 µF capacitors."+ },+ {+ "number": "34",+ "name": "AGND1",+ "type": "power_in",+ "description": "Analog ground for circuitry powered by AVDD1."+ },+ {+ "number": "35",+ "name": "DGND",+ "type": "power_in",+ "description": "Ground reference for digital circuitry."+ },+ {+ "number": "36",+ "name": "SYNC",+ "type": "input",+ "description": "Synchronization input; a falling edge resets the internal filter to synchronize multiple devices."+ },+ {+ "number": "37",+ "name": "RESET",+ "type": "input",+ "description": "A falling edge resets all internal digital circuitry and powers down the part; holding it low keeps the device in reset."+ },+ {+ "number": "38",+ "name": "DRDY",+ "type": "output",+ "description": "Data ready output that produces an active low pulse, ½ ICLK period wide, when new conversion data is available."+ },+ {+ "number": "39",+ "name": "RD/WR",+ "type": "input",+ "description": "Read/write input; with CS low, a low level causes a read and a high level causes a write."+ },+ {+ "number": "40",+ "name": "CS",+ "type": "input",+ "description": "Chip select input used with RD/WR to read and write data."+ },+ {+ "number": "41",+ "name": "DVDD",+ "type": "power_in",+ "description": "2.5 V power supply for digital circuitry and the FIR filter, decoupled to DGND with 100 nF."+ },+ {+ "number": "42",+ "name": "DGND",+ "type": "power_in",+ "description": "Ground reference for digital circuitry."+ },+ {+ "number": "43",+ "name": "DGND",+ "type": "power_in",+ "description": "Ground reference for digital circuitry."+ },+ {+ "number": "44",+ "name": "VDRIVE",+ "type": "power_in",+ "description": "Logic power supply input, 1.8 V to 2.5 V, that sets the logic interface voltage; must be tied together with pin 63."+ },+ {+ "number": "45",+ "name": "DB15",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 15; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "46",+ "name": "DB14",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 14; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "47",+ "name": "DB13",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 13; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "48",+ "name": "DB12",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 12; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "49",+ "name": "DB11",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 11; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "50",+ "name": "DB10",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 10; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "51",+ "name": "DB9",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 9; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "52",+ "name": "DB8",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 8; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "53",+ "name": "DGND",+ "type": "power_in",+ "description": "Ground reference for digital circuitry."+ },+ {+ "number": "54",+ "name": "DB7",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 7; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "55",+ "name": "DB6",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 6; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "56",+ "name": "DB5",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 5; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "57",+ "name": "DB4",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 4; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "58",+ "name": "DB3",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 3; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "59",+ "name": "DB2",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 2; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "60",+ "name": "DB1",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 1; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "61",+ "name": "DB0",+ "type": "bidirectional",+ "description": "16-bit bidirectional data bus bit 0; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE."+ },+ {+ "number": "62",+ "name": "DGND",+ "type": "power_in",+ "description": "Ground reference for digital circuitry."+ },+ {+ "number": "63",+ "name": "VDRIVE",+ "type": "power_in",+ "description": "Logic power supply input, 1.8 V to 2.5 V, that sets the logic interface voltage; must be tied together with pin 44."+ },+ {+ "number": "64",+ "name": "DGND",+ "type": "power_in",+ "description": "Ground reference for digital circuitry."+ },+ {+ "number": "65",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pinout taken from the 64-lead TQFP_EP entries in Table 5 and the pin list on pages 9-10; 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