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AD7760BSVZ

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Analog Devices Analog To Digital Converters (ADCs), TQFP-64-EP(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad7760bsvzfactory-2.0.0extractor-text

Verified AD7760BSVZ

by Ray · last 30 Oct 2026 · 1 record · files match
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Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 65 pinsfiles match
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  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD7760BSVZ · TQFP-64-EP(10x10) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 36-page datasheet
  • ✓distributor: lcsc C578509, digikey 505-AD7760BSVZ-ND, mouser 584-AD7760BSVZ
  • ✓family: TQFP-64-1EP_10x10mm_P0.5mm_EP5.305x5.305mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-72olmv28/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad7760bsvz.kicad_sym✓ ad7760bsvz.kicad_mod✓ ad7760bsvz.step
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Contents

README

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AD7760BSVZ

Analog Devices · Analog To Digital Converters (ADCs) · TQFP-64-EP(10x10)

AD7760BSVZ from Analog Devices, in a TQFP-64-EP(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DGND power_in Ground reference for digital circuitry.
2 MCLKGND power_in Master clock ground sensing pin.
3 MCLK input Low jitter, buffered digital master clock input; the output data rate depends on this clock frequency.
4 AVDD2 power_in 5 V power supply, decoupled to AGND2 with 100 nF capacitors on pins 4, 14 and 15.
5 AGND2 power_in Analog ground for circuitry powered by AVDD2.
6 AVDD1 power_in 2.5 V power supply for the modulator, decoupled to AGND1 with 100 nF and 10 µF capacitors.
7 AGND1 power_in Analog ground for circuitry powered by AVDD1.
8 DECAPA passive Decoupling pin; a 100 nF capacitor must be connected between this pin and AGND.
9 REFGND power_in Reference ground, the ground connection for the reference voltage.
10 VREF+ power_in Reference input whose input range is set by the reference buffer supply AVDD4.
11 AGND4 power_in Analog ground for circuitry powered by AVDD4.
12 AVDD4 power_in 3.3 V to 5 V power supply for the reference buffer, decoupled to pin 9 with 10 nF in series with 10 Ω.
13 AGND2 power_in Analog ground for circuitry powered by AVDD2.
14 AVDD2 power_in 5 V power supply, decoupled to AGND2 with a 100 nF capacitor.
15 AVDD2 power_in 5 V power supply, decoupled to AGND2 with a 100 nF capacitor.
16 AGND2 power_in Analog ground for circuitry powered by AVDD2.
17 RBIAS passive Bias current setting pin; a resistor must be connected between this pin and AGND.
18 AGND2 power_in Analog ground for circuitry powered by AVDD2.
19 VINA+ input Positive input to the on-chip differential amplifier.
20 VINA- input Negative input to the on-chip differential amplifier.
21 VOUTA- output Negative output from the differential amplifier.
22 VOUTA+ output Positive output from the differential amplifier.
23 AGND3 power_in Analog ground for circuitry powered by AVDD3.
24 AVDD3 power_in 3.3 V to 5 V power supply for the differential amplifier, decoupled to AGND3 with 100 nF.
25 VIN+ power_in Positive fully differential input to the modulator.
26 VIN- power_in Negative fully differential input to the modulator.
27 AVDD2 power_in 5 V power supply; connected to pin 14 via a 15 nH inductor.
28 AGND2 power_in Analog ground for circuitry powered by AVDD2.
29 AGND3 power_in Analog ground for circuitry powered by AVDD3.
30 DECAPB passive Decoupling pin; a 33 pF capacitor must be connected between this pin and AGND3.
31 AGND3 power_in Analog ground for circuitry powered by AVDD3.
32 AGND3 power_in Analog ground for circuitry powered by AVDD3.
33 AVDD1 power_in 2.5 V power supply for the modulator, decoupled to AGND1 with 100 nF and 10 µF capacitors.
34 AGND1 power_in Analog ground for circuitry powered by AVDD1.
35 DGND power_in Ground reference for digital circuitry.
36 SYNC input Synchronization input; a falling edge resets the internal filter to synchronize multiple devices.
37 RESET input A falling edge resets all internal digital circuitry and powers down the part; holding it low keeps the device in reset.
38 DRDY output Data ready output that produces an active low pulse, ½ ICLK period wide, when new conversion data is available.
39 RD/WR input Read/write input; with CS low, a low level causes a read and a high level causes a write.
40 CS input Chip select input used with RD/WR to read and write data.
41 DVDD power_in 2.5 V power supply for digital circuitry and the FIR filter, decoupled to DGND with 100 nF.
42 DGND power_in Ground reference for digital circuitry.
43 DGND power_in Ground reference for digital circuitry.
44 VDRIVE power_in Logic power supply input, 1.8 V to 2.5 V, that sets the logic interface voltage; must be tied together with pin 63.
45 DB15 bidirectional 16-bit bidirectional data bus bit 15; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE.
46 DB14 bidirectional 16-bit bidirectional data bus bit 14; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE.
47 DB13 bidirectional 16-bit bidirectional data bus bit 13; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE.
48 DB12 bidirectional 16-bit bidirectional data bus bit 12; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE.
49 DB11 bidirectional 16-bit bidirectional data bus bit 11; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE.
50 DB10 bidirectional 16-bit bidirectional data bus bit 10; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE.
51 DB9 bidirectional 16-bit bidirectional data bus bit 9; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE.
52 DB8 bidirectional 16-bit bidirectional data bus bit 8; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE.
53 DGND power_in Ground reference for digital circuitry.
54 DB7 bidirectional 16-bit bidirectional data bus bit 7; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE.
55 DB6 bidirectional 16-bit bidirectional data bus bit 6; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE.
56 DB5 bidirectional 16-bit bidirectional data bus bit 5; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE.
57 DB4 bidirectional 16-bit bidirectional data bus bit 4; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE.
58 DB3 bidirectional 16-bit bidirectional data bus bit 3; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE.
59 DB2 bidirectional 16-bit bidirectional data bus bit 2; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE.
60 DB1 bidirectional 16-bit bidirectional data bus bit 1; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE.
61 DB0 bidirectional 16-bit bidirectional data bus bit 0; three-state, controlled by CS and RD/WR, with operating voltage set by VDRIVE.
62 DGND power_in Ground reference for digital circuitry.
63 VDRIVE power_in Logic power supply input, 1.8 V to 2.5 V, that sets the logic interface voltage; must be tied together with pin 44.
64 DGND power_in Ground reference for digital circuitry.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TQFP-64-EP(10x10)
Category ADC/DAC/Data Conversion
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Dynamic Range (decimate by 256) 119 dB Modulator inputs shorted 4
Dynamic Range (decimate by 32) 108 dB Modulator inputs shorted 4
Dynamic Range (decimate by 8) 99 dB Modulator inputs shorted 4
Zero Error 0.014 0.02 % 4
VREF Input Voltage (VDD3 = 3.3 V ± 5%) VREF 2.5 V VDD3 = 3.3 V ± 5% 5
VREF Input Voltage (VDD3 = 5 V ± 5%) VREF 4.096 V VDD3 = 5 V ± 5% 5
VREF Input DC Leakage Current -6 6 µA 5
VREF Input Capacitance 5 pF 5
Total Power Dissipation (normal mode) 958 mW Normal mode 5
Total Power Dissipation (low power mode) 661 mW Low power mode 5
Standby Mode Power Dissipation 6.35 mW Clock stopped 5
AVDD1 (Modulator Supply) tolerance AVDD1 -5 5 % Nominal +2.5 V 5
AVDD2 (General Supply) tolerance AVDD2 -5 5 % Nominal +5 V 5
DVDD tolerance DVDD -5 5 % Nominal +2.5 V 5
AVDD3 (Differential Amplifier Supply) AVDD3 3.15 5.25 V 5
AVDD4 (Reference Buffer Supply) AVDD4 3.15 5.25 V 5
VDRIVE Logic Supply VDRIVE 1.65 2.7 V 5
AIDD1 (Modulator), normal mode AIDD1 49 51 mA Normal mode 5
AIDD2 (General), normal mode AIDD2 40 42 mA Normal mode 5
AIDD4 (Reference Buffer), normal mode AIDD4 34 36 mA AVDD4 = 5 V, normal mode 5
AIDD1 (Modulator), low power mode AIDD1 26 28 mA Low power mode 5
AIDD2 (General), low power mode AIDD2 20 23 mA Low power mode 5
AIDD4 (Reference Buffer), low power mode AIDD4 9 10 mA AVDD4 = 5 V, low power mode 5
AIDD3 (Differential Amplifier) AIDD3 41 44 mA AVDD3 = 5 V, both modes 5
DIDD DIDD 63 70 mA Both modes 5
Input Leakage Current -5 5 µA 5
Three-State Leakage Current (D15:D0) -5 5 µA 5
VINH Input High Voltage VINH 0.7 V × VDRIVE 5
VINL Input Low Voltage VINL 0.3 V × VDRIVE 5
VOH high-level output voltage VOH5 1.5 V Tested using minimum VDRIVE of 1.65 V with 400 µA load current 5
VOL low-level output voltage VOL4 0.1 V 5
Master clock frequency fMCLK fMCLK 1 40 MHz Applied master clock frequency 6
DRDY falling edge to CS falling edge t2 10 ns 6
RD/WR setup time to CS falling edge t3 3 ns 6
Bus relinquish time t8 11 ns 6
RD/WR hold time to CS rising edge t7 3 ns 6
Data valid prior to DRDY rising edge t12 23 ns Modulator output mode with CDIV = 1 6
Data valid after DRDY rising edge t13 19 ns Modulator output mode with CDIV = 1 6
Bus relinquish time (write) t14 11 ns 6
Data setup time t17 5 ns 6
Data hold time t18 0 ns 6
Data valid prior to MCLK falling edge while DRDY low t19 23 ns Modulator output mode with CDIV = 0 6
Data valid after MCLK falling edge while DRDY low t20 19 ns Modulator output mode with CDIV = 0 6
Voltage on any pin, AVDD1 to GND AVDD1 -0.3 3 V to GND 8
Voltage on AVDD2:AVDD4 to GND AVDD2:AVDD4 -0.3 6 V to GND 8
Voltage on DVDD to GND DVDD -0.3 3 V to GND 8
Voltage on VDRIVE to GND VDRIVE -0.3 3 V to GND 8
Voltage on VIN+, VIN− to GND VIN+, VIN− -0.3 6 V to GND 8
Voltage on VINA+, VINA− to GND VINA+, VINA− -0.3 6 V to GND 8
Voltage on MCLK to MCLKGND MCLK -0.3 6 V to MCLKGND 8
AGND to DGND voltage AGND -0.3 0.3 V to DGND 8
Input Current to Any Pin Except Supplies -10 10 mA 8
Operating Temperature Range (commercial) -40 85 °C Commercial 8
Storage Temperature Range -65 150 °C 8
Junction Temperature 150 °C 8
Lead Temperature, Vapor Phase 215 °C 60 sec 8
Lead Temperature, Infrared 220 °C 15 sec 8
θJA Thermal Impedance (TQFP exposed paddle) θJA 92.7 °C/W 8
θJC Thermal Impedance (TQFP exposed paddle) θJC 5.1 °C/W 8

CAD (KiCad official)

  • Symbol: AD7760BSVZ
  • Footprint: Package_QFP:TQFP-64-1EP_10x10mm_P0.5mm_EP5.305x5.305mm
  • 3D model: TQFP-64-EP(10x10) (KiCad packages3D, STEP)
  • 3D model files: ad7760bsvz-etched.step / ad7760bsvz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7760bsvz.step / ad7760bsvz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (36 pp, sha256 b78a13723854dcd1, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF