component
AD7747ARUZ-REEL
Public Made by Adomby adom
Analog Devices ADCs/DACs - Special Purpose, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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AD7747ARUZ-REEL
Analog Devices · ADCs/DACs - Special Purpose · TSSOP-16
AD7747ARUZ-REEL from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCL | input | Serial interface clock input that connects to the master clock line and requires a pull-up resistor if one is not already provided in the system. |
| 2 | RDY | output | Logic output whose falling edge indicates a finished conversion on the enabled channel(s); leave as an open circuit if not used. |
| 3 | SHLD | output | Capacitive input active AC shield used to shield the sensor connection and eliminate CIN parasitic capacitance to ground; leave as an open circuit if not used. |
| 4 | TST | unconnected | Test pin that must be left as an open circuit for proper operation. |
| 5 | REFIN(+) | input | Positive differential voltage reference input for the voltage (ADC) channel, not used for capacitive conversions; may be left open or connected to GND if not used. |
| 6 | REFIN(-) | input | Negative differential voltage reference input for the voltage (ADC) channel, not used for capacitive conversions; may be left open or connected to GND if not used. |
| 7 | CIN1(-) | passive | CDC negative capacitive input, with the measured capacitance connected between CIN1(-) and GND; leave as an open circuit if not used. |
| 8 | CIN1(+) | passive | CDC positive capacitive input, with the measured capacitance connected between CIN1(+) and GND; leave as an open circuit if not used. |
| 9 | NC | unconnected | Not connected; this pin should be left as an open circuit. |
| 10 | NC | unconnected | Not connected; this pin should be left as an open circuit. |
| 11 | VIN(+) | power_in | Positive differential voltage input for the voltage (ADC) channel that also connects an external temperature sensing diode; may be left open or connected to GND if not used. |
| 12 | VIN(-) | power_in | Negative differential voltage input for the voltage (ADC) channel that also connects an external temperature sensing diode; may be left open or connected to GND if not used. |
| 13 | GND | power_in | Ground pin. |
| 14 | VDD | power_in | Power supply voltage (2.7 V to 5.25 V operation), to be decoupled to GND with a low-impedance capacitor such as 10 µF tantalum in combination with 0.1 µF multilayer ceramic. |
| 15 | NC | unconnected | Not connected; this pin should be left as an open circuit. |
| 16 | SDA | bidirectional | Serial interface bidirectional data line that connects to the master data line and requires a pull-up resistor if not provided elsewhere in the system. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16 |
| Category | Data Acquisition |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Conversion Input Range | -8.192 | 8.192 | pF | Factory calibrated | 3 | ||
| Integral Nonlinearity (INL), capacitive input | INL | -0.01 | 0.01 | % of FSR | 3 | ||
| No Missing Codes, capacitive input | 24 | Bit | Conversion time ≥ 124 ms | 3 | |||
| Absolute Error | -10 | 10 | fF | 25°C, VDD = 5 V, after offset calibration | 3 | ||
| System Offset Calibration Range | -1 | 1 | pF | 3 | |||
| Gain Error | 0.02 | 0.11 | % of FS | 25°C, VDD = 5 V | 3 | ||
| Gain Drift vs. Temperature | -23 | -26 | -29 | ppm of FS/°C | 3 | ||
| Power Supply Rejection, capacitive input | 0.5 | 4 | fF/V | 3 | |||
| Normal Mode Rejection | 72 | dB | 50 Hz ± 1%, conversion time 124 ms | 3 | |||
| Normal Mode Rejection | 60 | dB | 60 Hz ± 1%, conversion time 124 ms | 3 | |||
| CAPDAC Full Range | 17 | 21 | pF | 6-bit CAPDAC | 3 | ||
| Temperature Sensor Error, internal sensor | -2 | 0.5 | 2 | °C | Internal temperature sensor, VREF internal | 3 | |
| Temperature Sensor Error, external sensing diode | -2 | 2 | °C | External sensing diode | 3 | ||
| Integral Nonlinearity (INL), voltage input | INL | -15 | 3 | 15 | ppm of FS | VREF internal or VREF = 2.5 V | 3 |
| No Missing Codes, voltage input | 24 | Bit | Conversion time = 122.1 ms | 3 | |||
| Offset Error, voltage input | -3 | 3 | μV | 3 | |||
| Full-Scale Error, voltage input | 0.025 | 0.1 | % of FS | 3 | |||
| Analog VIN Input Current Drift | -50 | 50 | pA/V/°C | 3 | |||
| Power Supply Rejection, voltage input | 80 | dB | Internal reference, VIN = VREF/2 | 3 | |||
| Power Supply Rejection, voltage input | 90 | dB | External reference, VIN = VREF/2 | 3 | |||
| SCL Frequency | fSCL | 0 | 400 | kHz | 5 | ||
| SCL High Pulse Width | tHIGH | 0.6 | μs | 5 | |||
| SCL Low Pulse Width | tLOW | 1.3 | μs | 5 | |||
| SCL, SDA Rise Time | tR | 0.3 | μs | 5 | |||
| SCL, SDA Fall Time | tF | 0.3 | μs | 5 | |||
| Hold Time (Start Condition) | tHD;STA | 0.6 | μs | After this period, the first clock is generated | 5 | ||
| Setup Time (Start Condition) | tSU;STA | 0.6 | μs | Relevant for repeated start condition | 5 | ||
| Data Setup Time | tSU;DAT | 0.1 | μs | 5 | |||
| Data Hold Time (Master) | tHD;DAT | 0 | μs | Master | 5 | ||
| Setup Time (Stop Condition) | tSU;STO | 0.6 | μs | 5 | |||
| Bus-Free Time (between Stop and Start Condition) | tBUF | 1.3 | μs | 5 | |||
| Positive Supply Voltage VDD to GND | VDD | -0.3 | 6.5 | V | 6 | ||
| Voltage on any Input or Output Pin to GND | -0.3 | V | 6 | ||||
| Operating Temperature Range | -40 | 125 | °C | 6 | |||
| Storage Temperature Range | -65 | 150 | °C | 6 | |||
| Junction Temperature | TJ | 150 | °C | 6 | |||
| Peak Reflow Soldering Temperature | 260 | °C | Pb free (20 sec to 40 sec) | 6 | |||
| TSSOP Package Thermal Impedance-to-Air | θJA | 128 | °C/W | TSSOP package | 6 | ||
| TSSOP Package Thermal Impedance-to-Case | θJC | 14 | °C/W | TSSOP package | 6 | ||
| Supply Voltage VDD | VDD | 2.7 | 3.6 | V | VDD = 2.7 V to 3.6 V range | 3 | |
| Supply Voltage VDD | VDD | 4.75 | 5.25 | V | VDD = 4.75 V to 5.25 V range | 3 | |
| Operating Temperature Range | -40 | 125 | °C | 3 |
CAD (KiCad official)
- Symbol:
AD7747ARUZ-REEL - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
ad7747aruz-reel-etched.step/ad7747aruz-reel-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7747aruz-reel.step/ad7747aruz-reel.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (28 pp, sha256
4d73ef988f6cb324, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).