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AD7740KRMZ-REEL7

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Analog Devices Voltage-to-Frequency / Frequency-to-Voltage Converters, MSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata convertersad7740krmz-reel7factory-2.0.0extractor-text

Verified AD7740KRMZ-REEL7

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD7740KRMZ-REEL7 · MSOP-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 12-page datasheet
  • ✓distributor: lcsc C84247, digikey 505-AD7740KRMZ-REEL7TR-ND, mouser 584-AD7740KRMZ-R7
  • ✓family: MSOP-8_3x3mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-88etoiww/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad7740krmz-reel7.kicad_sym✓ ad7740krmz-reel7.kicad_mod✓ ad7740krmz-reel7.step
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Ray Publish 0.1.0 a50c859 19h ago

AD7740KRMZ-REEL7

Analog Devices · Voltage-to-Frequency / Frequency-to-Voltage Converters · MSOP-8

AD7740KRMZ-REEL7 from Analog Devices, in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLKOUT output The crystal/resonator is tied between this pin and CLKIN; with an external clock on CLKIN an inverted clock appears here and must be buffered before driving other circuitry.
2 CLKIN input The master clock input accepts a crystal/resonator to CLKOUT or a CMOS-compatible clock, and the part enters power-down if CLKIN is inactive low for 1 ms (typ).
3 GND power_in Ground reference for all the circuitry on-chip.
4 REFIN/OUT bidirectional Voltage reference pin that defines the VFC span; it uses the internal 2.5 V reference when left unconnected, and an external reference must sink/source 400 µA to overdrive it.
5 VIN power_in Analog input with a nominal range of 0 V to VREF (±150 mV overrange) mapping to 10% to 90% of fCLKIN; in buffered mode the range is restricted to 0.1 V to VDD - 0.2 V.
6 VDD power_in Power supply input operated at 3.3 V ± 10% or 5 V ± 5%, to be decoupled with a 10 µF and a 0.1 µF capacitor to GND.
7 FOUT output Frequency output that goes from 10% to 90% of fCLKIN depending on VIN.
8 BUF input Buffered mode select: tied low gives unbuffered VIN range -0.15 V to VDD + 0.15 V, tied high gives buffered VIN range 0.1 V to VDD - 0.2 V.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package MSOP-8
Category Data Converters
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Offset Error (unbuffered) -35 7 35 mV Unbuffered Mode, VIN = 0 V 2
Offset Error (buffered) -35 7 35 mV Buffered Mode, VIN = 0.1 V 2
Gain Error -0.7 0.1 0.7 % of Span 2
Offset Error Drift -20 20 µV/°C 2
Gain Error Drift -4 4 ppm of Span/°C 2
Power Supply Rejection Ratio -55 dB ∆VDD = ±5% (5 V) 2
Power Supply Rejection Ratio -65 dB ∆VDD = ±10% (3.3 V) 2
Nominal Input Span overrange VIN -150 150 mV Overrange Available 2
Buffered Mode input range lower limit VIN 0.1 V Buffered Mode; upper limit VDD, 0.2 V 2
Input Current (unbuffered) 8 10 µA Unbuffered Mode, VIN = 5.4 V, REFIN = 5.25 V 2
Input Current (buffered) 5 100 nA Buffered Mode, VIN = 0.1 V, REFIN = 2.5 V 2
REFIN Nominal Input Voltage REFIN 2.5 V Nominal Input Voltage; upper limit VDD 2
REFOUT Output Voltage REFOUT 2.3 2.5 2.7 V 2
REFOUT Output Impedance 1 kΩ See Pin Function Description 2
Reference Drift -50 50 ppm/°C 2
Line Rejection -75 dB ∆VDD = ±5% (5 V) 2
Line Rejection -60 dB ∆VDD = ±10% (3.3 V) 2
Reference Noise (0.1 Hz to 10 Hz) 100 µV p-p 0.1 Hz to 10 Hz 2
CLKIN Input Frequency 32 1000 kHz For Specified Performance 2
CLKIN Input High Voltage VIH 3.5 V VDD = 5 V ± 5% 2
CLKIN Input High Voltage VIH 2.5 V VDD = 3.3 V ± 10% 2
CLKIN Input Low Voltage VIL 0.8 V VDD = 5 V ± 5% 2
CLKIN Input Low Voltage VIL 0.4 V VDD = 3.3 V ± 10% 2
CLKIN Input Current -2 2 µA VIN = 0 V to VDD 2
CLKIN Pin Capacitance 10 pF 2
BUF Input High Voltage VIH 2.4 V VDD = 5 V ± 5% 2
BUF Input High Voltage VIH 2.1 V VDD = 3.3 V ± 10% 2
BUF Input Low Voltage VIL 0.8 V VDD = 5 V ± 5% 2
BUF Input Low Voltage VIL 0.4 V VDD = 3.3 V ± 10% 2
BUF Input Current -100 100 nA 2
BUF Pin Capacitance 10 pF 2
Logic Output High Voltage (FOUT, CLKOUT) VOH 4 V Output Sourcing 200 µA. VDD = 5 V ± 5% 2
Logic Output High Voltage (FOUT, CLKOUT) VOH 2.1 V Output Sourcing 200 µA. VDD = 3.3 V ± 10% 2
Logic Output Low Voltage (FOUT, CLKOUT) VOL 0.1 0.4 V Output Sinking 1.6 mA 2
Supply Voltage VDD 3 5.25 V 2
IDD Normal Mode (unbuffered) IDD 0.9 1.25 mA VIH = VDD, VIL= GND. Unbuffered Mode 2
IDD Normal Mode (buffered) IDD 1.1 1.5 mA VIH = VDD, VIL= GND. Buffered Mode 2
IDD Power-Down IDD 30 100 µA 2
Power-Up Time 30 µs Exiting Power-Down (Ext. Clock at CLKIN) 2
Clock Frequency (VDD 3.0 V to 3.6 V and 4.75 V to 5.25 V) fCLKIN 32 kHz Clock Frequency 3
Clock Frequency (VDD 3.0 V to 3.6 V and 4.75 V to 5.25 V) fCLKIN 1 MHz Clock Frequency 3
VDD to GND VDD -0.3 7 V VDD to GND 3
Analog Input Voltage to GND VIN -0.3 V Analog Input Voltage to GND; upper limit VDD + 0.3 V 3
Reference Input Voltage to GND REFIN -0.3 V Reference Input Voltage to GND; upper limit VDD + 0.3 V 3
Logic Input Voltage to GND -0.3 V Logic Input Voltage to GND; upper limit VDD + 0.3 V 3
FOUT Voltage to GND FOUT -0.3 V FOUT Voltage to GND; upper limit VDD + 0.3 V 3
Operating Temperature Range (K Version) TA 0 85 °C Commercial (K Version) 3
Storage Temperature Range TSTG -65 150 °C 3
Junction Temperature (TJ Max) TJ 150 °C 3
Lead Temperature (10 secs) 300 °C 10 secs 3
MSOP Thermal Impedance (junction to ambient) θJA 206 °C/W MSOP Package 3
MSOP Thermal Impedance (junction to case) θJC 44 °C/W MSOP Package 3

CAD (KiCad official)

  • Symbol: AD7740KRMZ-REEL7
  • Footprint: Package_SO:MSOP-8_3x3mm_P0.65mm
  • 3D model: MSOP-8 (KiCad packages3D, STEP)
  • 3D model files: ad7740krmz-reel7-etched.step / ad7740krmz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7740krmz-reel7.step / ad7740krmz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (12 pp, sha256 fe4577e151525739, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF