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AD7739BRUZ-REEL7
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Analog Devices Analog To Digital Converters (ADCs), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Symbol & Footprint
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README
markdownAD7739BRUZ-REEL7
Analog Devices · Analog To Digital Converters (ADCs) · TSSOP-24
AD7739BRUZ-REEL7 from Analog Devices, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCLK | input | Serial clock Schmitt-triggered logic input used to transfer serial data to or from the AD7739. |
| 2 | MCLKIN | input | Master clock input that accepts a crystal/resonator across MCLKIN and MCLKOUT or a CMOS-compatible external clock. |
| 3 | MCLKOUT | output | Provides an inverted master clock when an external clock drives MCLKIN, can be switched off to reduce power, and can drive one CMOS load. |
| 4 | CS | input | Active-low Schmitt-triggered chip select with internal pull-up that selects the device on a shared serial bus and can act as an 8-bit frame sync. |
| 5 | RESET | input | Active-low Schmitt-triggered input that resets the control logic, interface, digital filter, modulator and all on-chip registers to power-on status. |
| 6 | AVDD | power_in | Analog positive supply, 5 V nominal with respect to AGND. |
| 7 | AINCOM/P0 | bidirectional | Analog inputs common terminal or digital I/O P0 (direction set by P0 DIR bit), referenced to the analog supplies; when used as an input it sets the reference level for AIN0 to AIN7. |
| 8 | SYNC/P1 | bidirectional | SYNC input or digital I/O P1 (direction set by P1 DIR bit), referenced to the analog supplies; when configured as an input it must be tied high or low. |
| 9 | AIN0 | passive | Analog input channel 0, single-ended to AINCOM or differential with AIN1. |
| 10 | AIN1 | passive | Analog input channel 1, single-ended to AINCOM or differential with AIN2/AIN3 pair per channel configuration. |
| 11 | AIN2 | passive | Analog input channel 2, single-ended to AINCOM or part of a differential pair with AIN4/AIN5 per channel configuration. |
| 12 | AIN3 | passive | Analog input channel 3, single-ended to AINCOM or part of a differential pair with AIN6/AIN7 per channel configuration. |
| 13 | AIN4 | passive | Analog input channel 4, single-ended to AINCOM or differential with AIN0/AIN1 per channel configuration. |
| 14 | AIN5 | passive | Analog input channel 5, single-ended to AINCOM or differential with AIN2/AIN3 per channel configuration. |
| 15 | AIN6 | passive | Analog input channel 6, single-ended to AINCOM or differential with AIN4/AIN5 per channel configuration. |
| 16 | AIN7 | passive | Analog input channel 7, single-ended to AINCOM or differential with AIN6/AIN7 per channel configuration. |
| 17 | REFIN(+) | passive | Positive terminal of the differential reference input, which may lie anywhere between AGND and AVDD and is normally connected to 2.5 V. |
| 18 | REFIN(-) | passive | Negative terminal of the differential reference input, which may lie anywhere between AGND and AVDD and is normally connected to 0 V. |
| 19 | AGND | power_in | Ground reference point for the analog circuitry. |
| 20 | RDY | output | Status output that falls to indicate unread conversion data (per RDYFN bit) or calibration completion. |
| 21 | DOUT | output | Serial data output from the output shift register, containing contents of any AD7739 register selected by the communications register. |
| 22 | DIN | input | Schmitt-triggered serial data input that writes to any AD7739 register selected by the communications register. |
| 23 | DVDD | power_in | Digital positive supply, 3 V or 5 V nominal (DVDD specified 2.7 V to 3.6 V or 5 V ±5%). |
| 24 | DGND | power_in | Ground reference point for the digital circuitry. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-24 |
| Category | Data Converters |
| Pins | 24 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Conversion Time Rate, chopping enabled | 372 | 11840 | Hz | Configure via conv. time register | 3 | ||
| Integral Nonlinearity (INL), chopping enabled | INL | -0.0015 | 0.0015 | % of FSR | 3 | ||
| Offset Error (Unipolar, Bipolar), chopping enabled | -10 | 10 | µV | Before calibration | 3 | ||
| Offset Drift vs. Temperature, chopping enabled | -25 | 25 | nV/°C | 3 | |||
| Gain Error, chopping enabled | -0.2 | 0.2 | % | Before calibration | 3 | ||
| Gain Drift vs. Temperature, chopping enabled | -2.5 | 2.5 | ppm of FS/°C | 3 | |||
| Common-Mode Rejection, chopping enabled | 80 | 95 | dB | At dc, AIN = 1 V | 3 | ||
| Power Supply Rejection, chopping enabled | 70 | 80 | dB | At dc, AIN = 1 V | 3 | ||
| No Missing Codes, chopping enabled | 24 | Bits | FW ≥ 12 (conversion time ≥ 290 μs) | 3 | |||
| Conversion Time Rate, chopping disabled | 737 | 15133 | Hz | Configure via conv. time register | 3 | ||
| Integral Nonlinearity (INL), chopping disabled | INL | -0.0015 | 0.0015 | % of FSR | 3 | ||
| Offset Error (Unipolar, Bipolar), chopping disabled | -1 | 1 | mV | Before calibration | 3 | ||
| Common-Mode Rejection, chopping disabled | 75 | dB | At dc, AIN = 1 V | 3 | |||
| Analog Input Slew Rate | 0.5 | V/conv. time | AIN absolute voltage > 3 V | 3 | |||
| AIN, AINCOM Input Current | 1 | 5 | nA | Only one channel, chop disabled | 3 | ||
| REFIN(+) to REFIN(−) Voltage | 2.475 | 2.5 | 2.525 | V | 4 | ||
| REFIN(+), REFIN(−) Common-Mode/Absolute Voltage | 0 | V | 4 | ||||
| Full-Scale Calibration Limit | 1.05 | × FS | 4 | ||||
| Zero-Scale Calibration Limit | -1.05 | × FS | 4 | ||||
| Input Span (system calibration) | 0.8 | 2.1 | × FS | 4 | |||
| Logic Input Current | -1 | 1 | µA | 4 | |||
| Input Current CS | -10 | 10 | µA | CS = DVDD | 4 | ||
| VT+ Schmitt Trigger Threshold, DVDD = 5 V | VT+ | 1.4 | 2 | V | DVDD = 5 V | 4 | |
| VT− Schmitt Trigger Threshold, DVDD = 5 V | VT− | 0.8 | 1.4 | V | DVDD = 5 V | 4 | |
| Schmitt Trigger Hysteresis (VT+ − VT−), DVDD = 5 V | VT+ − VT− | 0.3 | 0.85 | V | DVDD = 5 V | 4 | |
| Schmitt Trigger Hysteresis (VT+ − VT−), DVDD = 3 V | VT+ − VT− | 0.3 | 0.85 | V | DVDD = 3 V | 4 | |
| MCLK IN Input Current | -10 | 10 | µA | 4 | |||
| MCLK IN Input Low Voltage, DVDD = 5 V | VINL | 0.8 | V | DVDD = 5 V | 4 | ||
| MCLK IN Input High Voltage, DVDD = 5 V | VINH | 3.5 | V | DVDD = 5 V | 4 | ||
| Logic Output Low Voltage, DVDD = 5 V | VOL | 0.4 | V | ISINK = 800 μA, DVDD = 5 V | 4 | ||
| Logic Output High Voltage, DVDD = 5 V | VOH | 4 | V | ISOURCE = 200 μA, DVDD = 5 V | 4 | ||
| Logic Output Low Voltage, DVDD = 3 V | VOL | 0.4 | V | ISINK = 100 μA, DVDD = 3 V | 4 | ||
| Floating State Leakage Current | -1 | 1 | µA | 4 | |||
| P0, P1 Input Low Voltage | VINL | 0.8 | V | AVDD = 5 V | 4 | ||
| P0, P1 Input High Voltage | VINH | 3.5 | V | AVDD = 5 V | 4 | ||
| P0, P1 Output Low Voltage | VOL | 0.4 | V | ISINK = 8 mA, AVDD = 5 V | 4 | ||
| P0, P1 Output High Voltage | VOH | 4 | V | ISOURCE = 200 μA, AVDD = 5 V | 4 | ||
| AVDD to AGND Voltage | AVDD | 4.75 | 5.25 | V | 5 | ||
| DVDD to DGND Voltage (5 V ±5%) | DVDD | 4.75 | 5.25 | V | 5 | ||
| DVDD to DGND Voltage (2.7 V to 3.6 V) | DVDD | 2.7 | 3.6 | V | 5 | ||
| AVDD Current (Normal Mode) | IAVDD | 13.6 | 16 | mA | 5 | ||
| DVDD Current (Normal Mode), DVDD = 5 V | IDVDD | 2.7 | 3 | mA | DVDD = 5 V | 5 | |
| Power Dissipation (Normal Mode) | 85 | 100 | mW | 5 | |||
| Master Clock Range | fMCLKIN | 1 | 6.144 | MHz | 5 | ||
| t1 SYNC Pulse Width | t1 | 50 | ns | 5 | |||
| t2 RESET Pulse Width | t2 | 500 | ns | 5 | |||
| t5 SCLK Falling Edge to Data Valid Delay | t5 | 0 | 60 | ns | DVDD of 4.75 V to 5.25 V | 5 | |
| t5 SCLK Falling Edge to Data Valid Delay | t5 | 0 | 80 | ns | DVDD of 2.7 V to 3.3 V | 5 | |
| t6 SCLK High Pulse Width | t6 | 50 | ns | 5 | |||
| t7 SCLK Low Pulse Width | t7 | 50 | ns | 5 | |||
| t9 Bus Relinquish Time After SCLK Rising Edge | t9 | 10 | 80 | ns | 5 | ||
| t12 Data Valid to SCLK Rising Edge Setup Time | t12 | 30 | ns | 6 | |||
| AVDD to AGND, DVDD to DGND | -0.3 | 7 | V | 7 | |||
| AVDD to DVDD | -5 | 5 | V | 7 | |||
| AIN, AINCOM to AGND | -0.3 | V | Upper limit printed as AVDD + 0.3 V | 7 | |||
| Digital Input Voltage to DGND | -0.3 | V | Upper limit printed as DVDD + 0.3 V | 7 | |||
| Junction Temperature | TJ | 150 | °C | 7 | |||
| Operating Temperature Range | TA | -40 | 105 | °C | 7 | ||
| TSSOP Package Thermal Impedance | θJA | 128 | °C/W | TSSOP package | 7 |
CAD (KiCad official)
- Symbol:
AD7739BRUZ-REEL7 - Footprint:
Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm - 3D model: TSSOP-24 (KiCad packages3D, STEP)
- 3D model files:
ad7739bruz-reel7-etched.step/ad7739bruz-reel7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7739bruz-reel7.step/ad7739bruz-reel7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (32 pp, sha256
2ce68404cea1d833, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).