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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

AD7730BRZ-REEL

Analog Devices · Analog Front End (AFE) · SOIC-24-300mil

AD7730BRZ-REEL from Analog Devices, in a SOIC-24-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SCLK	input	Schmitt-triggered serial clock input for transferring serial data to or from the device, supporting both continuous and noncontinuous clock modes.
2	MCLK IN	input	Master clock signal input accepting crystal/resonator or external CMOS-compatible clock source at 4.9152 MHz nominal frequency for AD7730.
3	MCLK OUT	output	Master clock output providing inverted clock signal capable of driving one CMOS load; can be disabled with CLKDIS bit in Mode Register.
4	POL	input	Clock polarity logic input determining active SCLK edge; low for high-to-low active edge, high for low-to-high active edge.
5	SYNC	input	Synchronization logic input that resets digital filter and analog modulator when low, allowing synchronized operation of multiple devices.
6	RESET	input	Active-low logic input that resets all control logic, interface logic, digital filter, analog modulator, and on-chip registers to power-on status.
7	VBIAS	output	Internally-generated analog bias voltage output not intended for external use; do not connect external components to this pin.
8	AGND	power_in	Ground reference point for analog circuitry.
9	AVDD	power_in	Analog positive supply voltage, nominally +5 V with respect to AGND, operating range +4.75 V to +5.25 V.
10	AIN1(+)	input	Positive input of differential, programmable-gain primary analog input pair supporting unipolar ranges 0 to +10/20/40/80 mV and bipolar ranges ±10/20/40/80 mV with gains 250/125/62.5/31.25.
11	AIN1(-)	input	Negative input of differential, programmable-gain primary analog input pair with buffered high-impedance input stage.
12	AIN2(+)/D1	bidirectional	Secondary analog input channel positive input or digital output bit 1, selectable via DEN bit of Mode Register; programmable in range 0 to +10/20/40/80 mV unipolar or ±10/20/40/80 mV bipolar when configured as analog input.
13	AIN2(-)/D0	bidirectional	Secondary analog input channel negative input or digital output bit 0, selectable via DEN bit of Mode Register; output state programmable via D0 bit of Mode Register when configured as digital output.
14	REF IN(+)	input	Positive terminal of differential reference input accepting voltage from AGND to AVDD, nominal +5 V when HIREF bit is 1 or +2.5 V when HIREF bit is 0.
15	REF IN(-)	input	Negative terminal of differential reference input accepting voltage from AGND to AVDD for ratiometric operation.
16	ACX	output	AC excitation control digital output providing high signal during normal bridge excitation and low signal during reversed (chopped) excitation; remains high when AC mode or chop mode disabled.
17	ACX	output	Complement of ACX digital output, toggling in anti-phase with guaranteed nonoverlapping interval of one master clock cycle; remains low when AC mode or chop mode disabled.
18	STANDBY	input	Active-low logic input placing device in standby mode reducing total current consumption to 5 µA range while retaining all on-chip register values.
19	CS	input	Active-low chip select logic input enabling device selection; can be hardwired low for three-wire serial interface mode or used for multi-device bus selection and frame synchronization.
20	RDY	output	Ready status logic output indicating new data availability in conversion mode (low = new word available) and calibration completion; provides synchronization indication during calibration.
21	DOUT	output	Serial data output providing conversion results, calibration coefficients, or register contents as selected by Communications Register bits RS2-RS0.
22	DIN	input	Serial data input accepting serial command and configuration data to be written to device registers via serial interface with MSB first.
23	DVDD	power_in	Digital supply voltage, nominally +3 V or +5 V, operating range +2.7 V to +5.25 V with respect to DGND.
24	DGND	power_in	Ground reference point for digital circuitry.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	SOIC-24-300mil
Category	Data Acquisition
Pins	24

CAD (KiCad official)

Symbol: AD7730BRZ-REEL
Footprint: Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm
3D model: SOIC-24-300mil (KiCad packages3D, STEP)
3D model files: ad7730brz-reel-etched.step / ad7730brz-reel-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7730brz-reel.step / ad7730brz-reel.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (53 pp, sha256 71122c870f1183b1, retrieved 2026-09-21, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF