AD7709ARUZ from Analog Devices, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	IOUT1	output	Output for the internal excitation current sources IEXC1, IEXC2, IEXC3, or a combination of them, which can be switched to this pin.
2	IOUT2	output	Output for the internal excitation current sources IEXC1, IEXC2, IEXC3, or a combination of them, which can be switched to this pin.
3	REFIN1(+)	input	Positive reference input that can lie anywhere between VDD and GND + 1 V, with a nominal REFIN1 of 2.5 V and a functional range of 1 V to VDD.
4	REFIN1(-)	input	Negative reference input that can lie anywhere between GND and VDD - 1 V.
5	AIN1	input	Programmable-gain analog input used pseudo-differentially with AINCOM or as the positive input of a fully differential pair with AIN2.
6	AIN2	input	Programmable-gain analog input used pseudo-differentially with AINCOM or as the negative input of a fully differential pair with AIN1.
7	AIN3/P3	input	Programmable-gain analog input (positive input of a differential pair with AIN4, or pseudo-differential with AINCOM) that can also be programmed as a general-purpose digital input bit.
8	AIN4/P4	input	Programmable-gain analog input (negative input of a differential pair with AIN3, or pseudo-differential with AINCOM) that can also be programmed as a general-purpose digital input bit.
9	AINCOM	input	Reference point to which all analog inputs are referenced in pseudo-differential mode; absolute limits are GND - 30 mV to VDD + 30 mV.
10	REFIN2(+)	input	Positive reference input that can lie anywhere between VDD and GND + 1 V, with a nominal REFIN2 of 2.5 V and a functional range of 1 V to VDD.
11	REFIN2(-)	input	Negative reference input that can lie anywhere between GND and VDD - 1 V.
12	P2/SW2	output	Dual-purpose pin acting as a general-purpose output bit (P2) or as a low-side power switch (SW2) to PWRGND.
13	PWRGND	power_in	Ground point for the low-side power switches SW1 and SW2, which must be tied to GND.
14	P1/SW1	output	Dual-purpose pin acting as a general-purpose output bit (P1) or as a low-side power switch (SW1) to PWRGND.
15	RESET	input	Digital input that resets the ADC to its power-on-reset status, with a weak internal pull-up to VDD.
16	SCLK	input	Serial clock input for data transfers to and from the ADC, with a Schmitt-triggered input and a weak pull-up to VDD.
17	CS	input	Active-low chip select that selects the AD7709 on a shared serial bus or frames communications, and can be hardwired low for 3-wire operation; a weak pull-up to VDD is provided.
18	RDY	output	Logic-low status output that goes low when valid data is in the data register and returns high on completion of a data register read.
19	DOUT	output	Serial data output accessing the output shift register, which can contain data from any on-chip data or control register.
20	DIN	input	Serial data input to the input shift register, with a weak pull-up to VDD, whose contents are transferred to the control registers selected by the communications register.
21	GND	power_in	Ground reference point for the AD7709.
22	VDD	power_in	Supply voltage of 3 V or 5 V nominal (specified for 2.7 V to 3.6 V or 4.75 V to 5.25 V).
23	XTAL2	output	Output from the 32.768 kHz crystal oscillator inverter.
24	XTAL1	input	Input to the 32.768 kHz crystal oscillator inverter.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-24
Category	Data Converters
Pins	24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Output Update Rate		5.4		105	Hz	0.732 ms Increments	3
No Missing Codes		16			Bits	20 Hz Update Rate	3
Integral Nonlinearity		-30		30	ppm of FSR		3
Absolute AIN1-AIN4 Voltage Limits (min, GND + 100 mV)		100			mV		3
AIN1-AIN4 DC Input Current		-1		1	nA		3
Absolute AINCOM Voltage Limits (min, GND, 30 mV)		-30			mV		3
Normal-Mode Rejection @ 50 Hz		100			dB	50 Hz ± 1Hz, 16.65 Hz Update Rate, SF = 82	3
Normal-Mode Rejection @ 60 Hz		100			dB	60 Hz ± 1 Hz, 20 Hz Update Rate, SF = 68	3
Common-Mode Rejection @ 50 Hz		100			dB	50 Hz ± 1 Hz, Range = ±2.56 V, AIN = 1 V	3
Common-Mode Rejection @ 60 Hz		100			dB	60 Hz ± 1 Hz, Range = ±2.56 V, AIN = 1 V	3
REFIN Voltage Range (min)		1			V		3
Absolute REFIN Voltage Limits (min, GND, 30 mV)		-30			mV		3
REFIN Normal-Mode Rejection @ 50 Hz		100			dB	50 Hz ± 1 Hz, SF = 82	3
REFIN Normal-Mode Rejection @ 60 Hz		100			dB	60 Hz ± 1 Hz, SF = 68	3
Output Compliance (min, GND, 30 mV)		-30			mV		4
Logic Input Low Voltage (VINL)	VINL			0.8	V	VDD = 5 V	4
Logic Input Low Voltage (VINL)	VINL			0.4	V	VDD = 3 V	4
Logic Input High Voltage (VINH)	VINH	2			V	VDD = 3 V or 5 V	4
SCLK Schmitt Trigger Positive Threshold VT(+) at 5 V	VT(+)	1.4		2	V	VDD = 5 V	4
SCLK Schmitt Trigger Negative Threshold VT(-) at 5 V	VT(-)	0.8		1.4	V	VDD = 5 V	4
SCLK Schmitt Trigger Positive Threshold VT(+) at 3 V	VT(+)	0.95		2	V	VDD = 3 V	4
SCLK Schmitt Trigger Negative Threshold VT(-) at 3 V	VT(-)	0.4		1.1	V	VDD = 3 V	4
Input Currents (except XTAL)		-2		2	mA	VIN = VDD	4
Input Currents (except XTAL)				-70	mA	VIN = GND	4
Logic Output Low Voltage (VOL) at 3 V	VOL			0.4	V	VDD = 3 V, ISINK = 100 mA	5
Logic Output High Voltage (VOH) at 5 V	VOH	4			V	VDD = 5 V, ISOURCE = 200 mA	5
Logic Output Low Voltage (VOL) at 5 V	VOL			0.4	V	VDD = 5 V, ISINK = 1.6 mA	5
Floating-State Leakage Current		-10		10	mA		5
Power Supply Voltage (VDD, GND, 3 V nominal)	VDD	2.7		3.6	V	VDD = 3 V nom	5
Power Supply Voltage (VDD, GND, 5 V nominal)	VDD	4.75		5.25	V	VDD = 5 V nom	5
IDD Current	IDD		1.25	1.5	mA	VDD = 3 V	5
IDD Current	IDD		1.45	1.75	mA	VDD = 5 V	5
RESET Pulsewidth	t2	50			ns		6
RDY to CS Setup Time	t3	0			ns		6
CS Falling Edge to SCLK Active Edge Setup Time	t4	0			ns		6
SCLK Active Edge to Data Valid Delay	t5	0			ns		6
SCLK Active Edge to Data Valid Delay	t5			60	ns	VDD = 4.75 V to 5.25 V	6
SCLK Active Edge to Data Valid Delay	t5			80	ns	VDD = 2.7 V to 3.6 V	6
SCLK High Pulsewidth (read)	t6	100			ns		6
SCLK Low Pulsewidth (read)	t7	100			ns		6
Bus Relinquish Time after SCLK Inactive Edge	t9	10			ns		6
Bus Relinquish Time after SCLK Inactive Edge	t9			80	ns		6
SCLK Active Edge to RDY High	t10			100	ns		6
CS Falling Edge to SCLK Active Edge Setup Time (write)	t11	0			ns		6
Data Valid to SCLK Edge Setup Time	t12	30			ns		6
Data Valid to SCLK Edge Hold Time	t13	25			ns		6
SCLK High Pulsewidth (write)	t14	100			ns		6
SCLK Low Pulsewidth (write)	t15	100			ns		6
VDD to GND	VDD	-0.3		7	V		8
PWRGND to AGND		-20		20	mV		8
Analog Input Voltage to GND		-0.3			V		8
Reference Input Voltage to GND		-0.3			V		8
Total AIN/REFIN Current				30	mA	Indefinite	8
Digital Input Voltage to GND		-0.3			V		8
Digital Output Voltage to GND		-0.3			V		8
Operating Temperature Range		-40		85	°C		8
Storage Temperature Range		-65		150	°C		8
Junction Temperature				150	°C		8
Thermal Impedance, Junction-to-Ambient	θJA		97.9		°C/W	Listed under Absolute Maximum Ratings, no min/max given	8
Thermal Impedance, Junction-to-Case	θJC		14		°C/W	Listed under Absolute Maximum Ratings, no min/max given	8

CAD (KiCad official)

Symbol: AD7709ARUZ
Footprint: Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm
3D model: TSSOP-24 (KiCad packages3D, STEP)
3D model files: ad7709aruz-etched.step / ad7709aruz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7709aruz.step / ad7709aruz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (32 pp, sha256 9e90dd87efab435d, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD7709ARUZ

Verified AD7709ARUZ

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README