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AD7705BRUZ-REEL7
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Analog Devices Analog To Digital Converters (ADC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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README
markdownAD7705BRUZ-REEL7
Analog Devices · Analog To Digital Converters (ADC) · TSSOP-16
AD7705BRUZ-REEL7 from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCLK | input | Serial clock input with a Schmitt-trigger logic input that clocks serial data to and from the device, and it may be continuous or noncontinuous. |
| 2 | MCLK IN | input | Master clock input that accepts a crystal/resonator across MCLK IN and MCLK OUT or a CMOS-compatible external clock, with operation in the 500 kHz to 5 MHz range. |
| 3 | MCLK OUT | output | Provides an inverted copy of an external clock applied to MCLK IN, is capable of driving 1 CMOS load, and can be turned off via the CLKDIS bit of the clock register. |
| 4 | CS | input | Active-low chip select that selects the device; it can be hardwired low for 3-wire interface operation. |
| 5 | RESET | input | Active-low reset input that returns the control logic, interface logic, calibration coefficients, digital filter, and analog modulator to power-on status. |
| 6 | AIN2(+) | input | Positive input of the differential analog input pair AIN2(+)/AIN2(−) on the AD7705. |
| 7 | AIN1(+) | input | Positive input of the differential analog input pair AIN1(+)/AIN1(−) on the AD7705. |
| 8 | AIN1(−) | input | Negative input of the differential analog input pair AIN1(+)/AIN1(−) on the AD7705. |
| 9 | REF IN(+) | input | Positive input of the differential reference, which must be greater than REF IN(−) and can lie anywhere between VDD and GND. |
| 10 | REF IN(−) | input | Negative input of the differential reference, which can lie anywhere between VDD and GND provided REF IN(+) is greater than REF IN(−). |
| 11 | AIN2(−) | input | Negative input of the differential analog input pair AIN2(+)/AIN2(−) on the AD7705. |
| 12 | DRDY | output | Logic output that goes low when a new output word is available in the data register, returns high after a full word is read, and also indicates completion of on-chip calibration. |
| 13 | DOUT | output | Serial data output that shifts out data from the setup, communication, clock, or data register as selected by the communication register. |
| 14 | DIN | input | Serial data input that writes data to the setup, clock, or communication register as selected by the communication register bits. |
| 15 | VDD | power_in | Supply voltage pin; the datasheet states 2.7 V to 5.25 V operation. |
| 16 | GND | power_in | Ground reference point for the device's internal circuitry. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16 |
| Category | Data Acquisition |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD supply voltage (3 V range) | VDD | 2.7 | 3.3 | V | For specified performance | 7 | |
| VDD supply voltage (5 V range) | VDD | 4.75 | 5.25 | V | For specified performance | 7 | |
| Power supply current, 3 V | IDD | 0.32 | mA | VDD 2.7-3.3 V; BUF=0, fCLKIN=1 MHz, gains 1 to 128; digital I/Ps 0 V or VDD, external MCLK IN, CLKDIS=1 | 7 | ||
| Power supply current, 3 V | IDD | 0.6 | mA | VDD 2.7-3.3 V; BUF=1, fCLKIN=1 MHz, gains 1 to 128; digital I/Ps 0 V or VDD, external MCLK IN, CLKDIS=1 | 7 | ||
| Power supply current, 3 V | IDD | 0.4 | mA | VDD 2.7-3.3 V; BUF=0, fCLKIN=2.4576 MHz, gains 1 to 4; digital I/Ps 0 V or VDD, external MCLK IN, CLKDIS=1 | 7 | ||
| Power supply current, 3 V | IDD | 0.7 | mA | VDD 2.7-3.3 V; BUF=1, fCLKIN=2.4576 MHz, gains 1 to 4; digital I/Ps 0 V or VDD, external MCLK IN, CLKDIS=1 | 7 | ||
| Power supply current, 3 V | IDD | 1.1 | mA | VDD 2.7-3.3 V; BUF=1, fCLKIN=2.4576 MHz, gains 8 to 128; digital I/Ps 0 V or VDD, external MCLK IN, CLKDIS=1 | 7 | ||
| Power supply current, 5 V | IDD | 0.45 | mA | VDD 4.75-5.25 V; BUF=0, fCLKIN=1 MHz, gains 1 to 128; digital I/Ps 0 V or VDD, external MCLK IN, CLKDIS=1 | 7 | ||
| Power supply current, 5 V | IDD | 0.7 | mA | VDD 4.75-5.25 V; BUF=1, fCLKIN=1 MHz, gains 1 to 128; digital I/Ps 0 V or VDD, external MCLK IN, CLKDIS=1 | 7 | ||
| Power supply current, 5 V | IDD | 0.6 | mA | VDD 4.75-5.25 V; BUF=0, fCLKIN=2.4576 MHz, gains 1 to 4; digital I/Ps 0 V or VDD, external MCLK IN, CLKDIS=1 | 7 | ||
| Power supply current, 5 V | IDD | 0.85 | mA | VDD 4.75-5.25 V; BUF=0, fCLKIN=2.4576 MHz, gains 8 to 128; digital I/Ps 0 V or VDD, external MCLK IN, CLKDIS=1 | 7 | ||
| Power supply current, 5 V | IDD | 0.9 | mA | VDD 4.75-5.25 V; BUF=1, fCLKIN=2.4576 MHz, gains 1 to 4; digital I/Ps 0 V or VDD, external MCLK IN, CLKDIS=1 | 7 | ||
| Power supply current, 5 V | IDD | 1.3 | mA | VDD 4.75-5.25 V; BUF=1, fCLKIN=2.4576 MHz, gains 8 to 128; digital I/Ps 0 V or VDD, external MCLK IN, CLKDIS=1 | 7 | ||
| Standby (power-down) current, 5 V | 16 | μA | VDD = 5 V; external MCLK IN = 0 V or VDD | 7 | |||
| Standby (power-down) current, 3 V | 8 | μA | VDD = 3 V; external MCLK IN = 0 V or VDD | 7 | |||
| Analog input voltage (absolute) for specified performance | -100 | mV | Absolute voltage on analog inputs for specified performance; upper limit printed as VDD + 30 mV | 7 | |||
| Master clock frequency (min) | fCLKIN | 400 | kHz | Crystal oscillator or externally supplied | 8 | ||
| Master clock frequency (max) | fCLKIN | 2.5 | MHz | For specified performance | 8 | ||
| Master clock input low time | tCLKIN LO | 0.4 | x tCLKIN | tCLKIN = 1/fCLKIN; printed as 0.4 × tCLKIN ns min | 8 | ||
| Master clock input high time | tCLKIN HI | 0.4 | x tCLKIN | tCLKIN = 1/fCLKIN; printed as 0.4 × tCLKIN ns min | 8 | ||
| RESET pulse width | t2 | 100 | ns | 8 | |||
| DRDY to CS setup time | t3 | 0 | ns | 8 | |||
| CS falling edge to SCLK rising edge setup time (read) | t4 | 120 | ns | 8 | |||
| SCLK falling edge to data valid delay (min) | t5 | 0 | ns | 8 | |||
| SCLK falling edge to data valid delay (max, 5 V) | t5 | 80 | ns | VDD = 5 V | 8 | ||
| SCLK falling edge to data valid delay (max, 3 V) | t5 | 100 | ns | VDD = 3.0 V | 8 | ||
| SCLK high pulse width (read) | t6 | 100 | ns | 8 | |||
| SCLK low pulse width (read) | t7 | 100 | ns | 8 | |||
| CS rising edge to SCLK rising edge hold time (read) | t8 | 0 | ns | 8 | |||
| Bus relinquish time after SCLK rising edge (min) | t9 | 10 | ns | 8 | |||
| Bus relinquish time after SCLK rising edge (max, 5 V) | t9 | 60 | ns | VDD = 5 V | 8 | ||
| Bus relinquish time after SCLK rising edge (max, 3 V) | t9 | 100 | ns | VDD = 3.0 V | 8 | ||
| SCLK falling edge to DRDY high | t10 | 100 | ns | 8 | |||
| CS falling edge to SCLK rising edge setup time (write) | t11 | 120 | ns | 8 | |||
| Data valid to SCLK rising edge setup time (write) | t12 | 30 | ns | 8 | |||
| Data valid to SCLK rising edge hold time (write) | t13 | 20 | ns | 8 | |||
| SCLK high pulse width (write) | t14 | 100 | ns | 8 | |||
| SCLK low pulse width (write) | t15 | 100 | ns | 8 | |||
| CS rising edge to SCLK rising edge hold time (write) | t16 | 0 | ns | 8 | |||
| VDD to GND | VDD | -0.3 | 7 | V | Voltage to GND | 9 | |
| Analog input voltage to GND | -0.3 | V | Upper limit printed as VDD + 0.3 V | 9 | |||
| Reference input voltage to GND | -0.3 | V | Upper limit printed as VDD + 0.3 V | 9 | |||
| Digital input voltage to GND | -0.3 | V | Upper limit printed as VDD + 0.3 V | 9 | |||
| Digital output voltage to GND | -0.3 | V | Upper limit printed as VDD + 0.3 V | 9 | |||
| Operating temperature range (commercial, B version) | TA | -40 | 85 | °C | Commercial (B version) | 9 | |
| Storage temperature range | -65 | 150 | °C | 9 | |||
| Junction temperature | TJ | 150 | °C | 9 | |||
| Power dissipation (SSOP package, as printed) | 450 | mW | Package listed as SSOP in Table 3 | 9 | |||
| Thermal impedance θJA (SSOP package, as printed) | θJA | 139 | °C/W | Package listed as SSOP in Table 3 | 9 | ||
| Lead temperature, vapor phase soldering (60 s) | 215 | °C | Vapor phase, 60 sec; SSOP package as printed | 9 | |||
| Lead temperature, infrared soldering (15 s) | 220 | °C | Infrared, 15 sec; SSOP package as printed | 9 | |||
| ESD rating | 4000 | V | Printed as >4000 V | 9 | |||
| Reference input dc leakage current | -1 | 1 | nA | Maximum dc input leakage on REF IN inputs, over temperature | 23 |
CAD (KiCad official)
- Symbol:
AD7705BRUZ-REEL7 - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
ad7705bruz-reel7-etched.step/ad7705bruz-reel7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7705bruz-reel7.step/ad7705bruz-reel7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (44 pp, sha256
822cb538aa5c64e3, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).