AD7705BRUZ-REEL

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  "slug": "ad7705bruz-reel",
  "title": "AD7705BRUZ-REEL",
  "brief": "Analog Devices Analog To Digital Converters (ADC), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
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  "component": {
    "mpn": "AD7705BRUZ-REEL",
    "manufacturer": "Analog Devices",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Data Acquisition",
    "subcategory": "Analog To Digital Converters (ADC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588883756014428160",
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    "distributor_links": {
      "lcsc": "C9678",
      "digikey": "505-AD7705BRUZ-REELTR-ND",
      "mouser": "584-AD7705BRUZ-R"
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        "status": "found",
        "lifecycle": "Restricted Availability"
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    },
    "pins": [
      {
        "number": "1",
        "name": "SCLK",
        "type": "input",
        "description": "Schmitt-triggered serial clock input used to access serial data, which may be a continuous or non-continuous clock."
      },
      {
        "number": "2",
        "name": "MCLK IN",
        "type": "input",
        "description": "Master clock input that accepts a crystal/resonator across MCLK IN and MCLK OUT or a CMOS-compatible external clock, with operating clock frequencies from 500 kHz to 5 MHz."
      },
      {
        "number": "3",
        "name": "MCLK OUT",
        "type": "output",
        "description": "Provides an inverted clock when an external clock drives MCLK IN, is capable of driving 1 CMOS load, and can be turned off via the CLKDIS bit of the clock register."
      },
      {
        "number": "4",
        "name": "CS",
        "type": "input",
        "description": "Active-low chip select input that selects the device; it can be hardwired low for 3-wire interface operation."
      },
      {
        "number": "5",
        "name": "RESET",
        "type": "input",
        "description": "Active-low input that resets the control logic, interface logic, calibration coefficients, digital filter and analog modulator to power-on status."
      },
      {
        "number": "6",
        "name": "AIN2(+)",
        "type": "input",
        "description": "Positive input of the differential analog input pair AIN2(+)/AIN2(-) on the AD7705."
      },
      {
        "number": "7",
        "name": "AIN1(+)",
        "type": "input",
        "description": "Positive input of the differential analog input pair AIN1(+)/AIN1(-) on the AD7705."
      },
      {
        "number": "8",
        "name": "AIN1(−)",
        "type": "input",
        "description": "Negative input of the differential analog input pair AIN1(+)/AIN1(-) on the AD7705."
      },
      {
        "number": "9",
        "name": "REF IN(+)",
        "type": "input",
        "description": "Positive input of the differential reference input, which must be greater than REF IN(-) and can lie anywhere between VDD and GND."
      },
      {
        "number": "10",
        "name": "REF IN(−)",
        "type": "input",
        "description": "Negative input of the differential reference input, which can lie anywhere between VDD and GND provided REF IN(+) is greater than REF IN(-)."
      },
      {
        "number": "11",
        "name": "AIN2(−)",
        "type": "input",
        "description": "Negative input of the differential analog input pair AIN2(+)/AIN2(-) on the AD7705."
      },
      {
        "number": "12",
        "name": "DRDY",
        "type": "output",
        "description": "Logic output that goes low when a new output word is available in the data register, returns high after a full word is read, and also indicates completion of on-chip calibration."
      },
      {
        "number": "13",
        "name": "DOUT",
        "type": "output",
        "description": "Serial data output from the output shift register, which can contain setup, communication, clock or data register contents depending on register selection bits."
      },
      {
        "number": "14",
        "name": "DIN",
        "type": "input",
        "description": "Serial data input to the input shift register, transferred to the setup, clock or communication register depending on the register selection bits."
      },
      {
        "number": "15",
        "name": "VDD",
        "type": "power_in",
        "description": "Supply voltage, 2.7 V to 5.25 V operation."
      },
      {
        "number": "16",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference point for the internal circuitry of the device."
      }
    ],
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        "primary_mode": "text",
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        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The datasheet has one generic 'AD7705 TOP VIEW' pin configuration figure and a Table 4 that covers t"
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        "cost_usd": 0.0711,
        "at": "2026-10-20T21:08:30"
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        "total": 16,
        "described": 16,
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  "metadata": {
    "specs": {
      "Manufacturer": "Analog Devices",
      "Package": "TSSOP-16",
      "Category": "Data Acquisition",
      "Pins": "16"
    },
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          "name": "VDD voltage (3 V operation)",
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        {
          "name": "VDD voltage (5 V operation)",
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        {
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          "name": "Master clock input low time",
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        {
          "name": "RESET pulse width",
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          "min": 100,
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          "max": null,
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        {
          "name": "DRDY to CS setup time",
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          "unit": "ns",
          "min": 0,
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          "max": null,
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        {
          "name": "CS falling edge to SCLK rising edge setup time (read)",
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          "kind": "timing",
          "unit": "ns",
          "min": 120,
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        {
          "name": "SCLK falling edge to data valid delay",
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          "kind": "timing",
          "unit": "ns",
          "min": 0,
          "typ": null,
          "max": null,
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          "source_page": 8,
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        {
          "name": "SCLK falling edge to data valid delay",
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          "kind": "timing",
          "unit": "ns",
          "min": null,
          "typ": null,
          "max": 80,
          "conditions": "VDD = 5 V",
          "source_page": 8,
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        {
          "name": "SCLK falling edge to data valid delay",
          "symbol": "t5",
          "kind": "timing",
          "unit": "ns",
          "min": null,
          "typ": null,
          "max": 100,
          "conditions": "VDD = 3.0 V",
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        {
          "name": "SCLK high pulse width",
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          "kind": "timing",
          "unit": "ns",
          "min": 100,
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          "max": null,
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          "source_page": 8,
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        {
          "name": "SCLK low pulse width",
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          "kind": "timing",
          "unit": "ns",
          "min": 100,
          "typ": null,
          "max": null,
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          "source_page": 8,
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        {
          "name": "CS rising edge to SCLK rising edge hold time",
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          "kind": "timing",
          "unit": "ns",
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          "typ": null,
          "max": null,
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          "source_page": 8,
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        {
          "name": "Bus relinquish time after SCLK rising edge",
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          "kind": "timing",
          "unit": "ns",
          "min": 10,
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        {
          "name": "Bus relinquish time after SCLK rising edge",
          "symbol": "t9",
          "kind": "timing",
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          "min": null,
          "typ": null,
          "max": 60,
          "conditions": "VDD = 5 V",
          "source_page": 8,
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        {
          "name": "Bus relinquish time after SCLK rising edge",
          "symbol": "t9",
          "kind": "timing",
          "unit": "ns",
          "min": null,
          "typ": null,
          "max": 100,
          "conditions": "VDD = 3.0 V",
          "source_page": 8,
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        },
        {
          "name": "SCLK falling edge to DRDY high",
          "symbol": "t10",
          "kind": "timing",
          "unit": "ns",
          "min": null,
          "typ": null,
          "max": 100,
          "conditions": "",
          "source_page": 8,
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        {
          "name": "CS falling edge to SCLK rising edge setup time (write)",
          "symbol": "t11",
          "kind": "timing",
          "unit": "ns",
          "min": 120,
          "typ": null,
          "max": null,
          "conditions": "",
          "source_page": 8,
          "source": "datasheet"
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        {
          "name": "Data valid to SCLK rising edge setup time",
          "symbol": "t12",
          "kind": "timing",
          "unit": "ns",
          "min": 30,
          "typ": null,
          "max": null,
          "conditions": "",
          "source_page": 8,
          "source": "datasheet"
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        {
          "name": "Data valid to SCLK rising edge hold time",
          "symbol": "t13",
          "kind": "timing",
          "unit": "ns",
          "min": 20,
          "typ": null,
          "max": null,
          "conditions": "",
          "source_page": 8,
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        {
          "name": "SCLK high pulse width (write)",
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          "kind": "timing",
          "unit": "ns",
          "min": 100,
          "typ": null,
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          "source_page": 8,
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        {
          "name": "SCLK low pulse width (write)",
          "symbol": "t15",
          "kind": "timing",
          "unit": "ns",
          "min": 100,
          "typ": null,
          "max": null,
          "conditions": "",
          "source_page": 8,
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        {
          "name": "CS rising edge to SCLK rising edge hold time (write)",
          "symbol": "t16",
          "kind": "timing",
          "unit": "ns",
          "min": 0,
          "typ": null,
          "max": null,
          "conditions": "",
          "source_page": 8,
          "source": "datasheet"
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        {
          "name": "Power supply current (BUF = 0, 1 MHz, gains 1 to 128)",
          "symbol": "IDD",
          "kind": "electrical",
          "unit": "mA",
          "min": null,
          "typ": null,
          "max": 0.32,
          "conditions": "VDD = 3 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 0, fCLKIN = 1 MHz, gains 1 to 128",
          "source_page": 7,
          "source": "datasheet"
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        {
          "name": "Power supply current (BUF = 1, 1 MHz, gains 1 to 128)",
          "symbol": "IDD",
          "kind": "electrical",
          "unit": "mA",
          "min": null,
          "typ": null,
          "max": 0.6,
          "conditions": "VDD = 3 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 1, fCLKIN = 1 MHz, gains 1 to 128",
          "source_page": 7,
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        {
          "name": "Power supply current (BUF = 0, 2.4576 MHz, gains 1 to 4)",
          "symbol": "IDD",
          "kind": "electrical",
          "unit": "mA",
          "min": null,
          "typ": null,
          "max": 0.4,
          "conditions": "VDD = 3 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 0, fCLKIN = 2.4576 MHz, gains 1 to 4",
          "source_page": 7,
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        {
          "name": "Power supply current (BUF = 0, 2.4576 MHz, gains 8 to 128)",
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          "conditions": "VDD = 3 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 0, fCLKIN = 2.4576 MHz, gains 8 to 128",
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        {
          "name": "Power supply current (BUF = 1, 2.4576 MHz, gains 1 to 4)",
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          "conditions": "VDD = 3 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 1, fCLKIN = 2.4576 MHz, gains 1 to 4",
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        {
          "name": "Power supply current (BUF = 1, 2.4576 MHz, gains 8 to 128)",
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          "min": null,
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          "max": 1.1,
          "conditions": "VDD = 3 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 1, fCLKIN = 2.4576 MHz, gains 8 to 128",
          "source_page": 7,
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        {
          "name": "Power supply current (BUF = 0, 1 MHz, gains 1 to 128)",
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          "min": null,
          "typ": null,
          "max": 0.45,
          "conditions": "VDD = 5 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 0, fCLKIN = 1 MHz, gains 1 to 128",
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          "name": "Power supply current (BUF = 1, 1 MHz, gains 1 to 128)",
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          "conditions": "VDD = 5 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 1, fCLKIN = 1 MHz, gains 1 to 128",
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          "name": "Power supply current (BUF = 0, 2.4576 MHz, gains 1 to 4)",
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          "conditions": "VDD = 5 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 0, fCLKIN = 2.4576 MHz, gains 1 to 4",
          "source_page": 7,
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        {
          "name": "Power supply current (BUF = 0, 2.4576 MHz, gains 8 to 128)",
          "symbol": "IDD",
          "kind": "electrical",
          "unit": "mA",
          "min": null,
          "typ": null,
          "max": 0.85,
          "conditions": "VDD = 5 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 0, fCLKIN = 2.4576 MHz, gains 8 to 128",
          "source_page": 7,
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        {
          "name": "Power supply current (BUF = 1, 2.4576 MHz, gains 1 to 4)",
          "symbol": "IDD",
          "kind": "electrical",
          "unit": "mA",
          "min": null,
          "typ": null,
          "max": 0.9,
          "conditions": "VDD = 5 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 1, fCLKIN = 2.4576 MHz, gains 1 to 4",
          "source_page": 7,
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        {
          "name": "Power supply current (BUF = 1, 2.4576 MHz, gains 8 to 128)",
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          "min": null,
          "typ": null,
          "max": 1.3,
          "conditions": "VDD = 5 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 1, fCLKIN = 2.4576 MHz, gains 8 to 128",
          "source_page": 7,
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        {
          "name": "Standby (power-down) current",
          "symbol": "IDD",
          "kind": "electrical",
          "unit": "μA",
          "min": null,
          "typ": null,
          "max": 16,
          "conditions": "VDD = 5 V; external MCLK IN = 0 V or VDD",
          "source_page": 7,
          "source": "datasheet"
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        {
          "name": "Standby (power-down) current",
          "symbol": "IDD",
          "kind": "electrical",
          "unit": "μA",
          "min": null,
          "typ": null,
          "max": 8,
          "conditions": "VDD = 3 V; external MCLK IN = 0 V or VDD",
          "source_page": 7,
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        {
          "name": "VDD to GND",
          "symbol": "VDD",
          "kind": "absolute_maximum",
          "unit": "V",
          "min": -0.3,
          "typ": null,
          "max": 7,
          "conditions": "",
          "source_page": 9,
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        {
          "name": "Analog input voltage to GND",
          "symbol": "",
          "kind": "absolute_maximum",
          "unit": "V",
          "min": -0.3,
          "typ": null,
          "max": null,
          "conditions": "Printed as VDD + 0.3 V; numeric max not applicable",
          "source_page": 9,
          "source": "datasheet"
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        {
          "name": "Reference input voltage to GND",
          "symbol": "",
          "kind": "absolute_maximum",
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          "min": -0.3,
          "typ": null,
          "max": null,
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