AD7705BRUZ-REEL

Analog Devices · Analog To Digital Converters (ADC) · TSSOP-16

AD7705BRUZ-REEL from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SCLK	input	Schmitt-triggered serial clock input used to access serial data, which may be a continuous or non-continuous clock.
2	MCLK IN	input	Master clock input that accepts a crystal/resonator across MCLK IN and MCLK OUT or a CMOS-compatible external clock, with operating clock frequencies from 500 kHz to 5 MHz.
3	MCLK OUT	output	Provides an inverted clock when an external clock drives MCLK IN, is capable of driving 1 CMOS load, and can be turned off via the CLKDIS bit of the clock register.
4	CS	input	Active-low chip select input that selects the device; it can be hardwired low for 3-wire interface operation.
5	RESET	input	Active-low input that resets the control logic, interface logic, calibration coefficients, digital filter and analog modulator to power-on status.
6	AIN2(+)	input	Positive input of the differential analog input pair AIN2(+)/AIN2(-) on the AD7705.
7	AIN1(+)	input	Positive input of the differential analog input pair AIN1(+)/AIN1(-) on the AD7705.
8	AIN1(−)	input	Negative input of the differential analog input pair AIN1(+)/AIN1(-) on the AD7705.
9	REF IN(+)	input	Positive input of the differential reference input, which must be greater than REF IN(-) and can lie anywhere between VDD and GND.
10	REF IN(−)	input	Negative input of the differential reference input, which can lie anywhere between VDD and GND provided REF IN(+) is greater than REF IN(-).
11	AIN2(−)	input	Negative input of the differential analog input pair AIN2(+)/AIN2(-) on the AD7705.
12	DRDY	output	Logic output that goes low when a new output word is available in the data register, returns high after a full word is read, and also indicates completion of on-chip calibration.
13	DOUT	output	Serial data output from the output shift register, which can contain setup, communication, clock or data register contents depending on register selection bits.
14	DIN	input	Serial data input to the input shift register, transferred to the setup, clock or communication register depending on the register selection bits.
15	VDD	power_in	Supply voltage, 2.7 V to 5.25 V operation.
16	GND	power_in	Ground reference point for the internal circuitry of the device.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	TSSOP-16
Category	Data Acquisition
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VDD voltage (3 V operation)	VDD	2.7		3.3	V	For specified performance	7
VDD voltage (5 V operation)	VDD	4.75		5.25	V	For specified performance	7
Master clock frequency	fCLKIN	400			kHz	Crystal oscillator or externally supplied	8
Master clock frequency	fCLKIN			2.5	MHz	For specified performance	8
Master clock input low time	tCLKIN LO	0.4			× tCLKIN ns	tCLKIN = 1/fCLKIN; printed as 0.4 × tCLKIN ns min	8
Master clock input high time	tCLKIN HI	0.4			× tCLKIN ns	tCLKIN = 1/fCLKIN; printed as 0.4 × tCLKIN ns min	8
RESET pulse width	t2	100			ns		8
DRDY to CS setup time	t3	0			ns		8
CS falling edge to SCLK rising edge setup time (read)	t4	120			ns		8
SCLK falling edge to data valid delay	t5	0			ns		8
SCLK falling edge to data valid delay	t5			80	ns	VDD = 5 V	8
SCLK falling edge to data valid delay	t5			100	ns	VDD = 3.0 V	8
SCLK high pulse width	t6	100			ns		8
SCLK low pulse width	t7	100			ns		8
CS rising edge to SCLK rising edge hold time	t8	0			ns		8
Bus relinquish time after SCLK rising edge	t9	10			ns		8
Bus relinquish time after SCLK rising edge	t9			60	ns	VDD = 5 V	8
Bus relinquish time after SCLK rising edge	t9			100	ns	VDD = 3.0 V	8
SCLK falling edge to DRDY high	t10			100	ns		8
CS falling edge to SCLK rising edge setup time (write)	t11	120			ns		8
Data valid to SCLK rising edge setup time	t12	30			ns		8
Data valid to SCLK rising edge hold time	t13	20			ns		8
SCLK high pulse width (write)	t14	100			ns		8
SCLK low pulse width (write)	t15	100			ns		8
CS rising edge to SCLK rising edge hold time (write)	t16	0			ns		8
Power supply current (BUF = 0, 1 MHz, gains 1 to 128)	IDD			0.32	mA	VDD = 3 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 0, fCLKIN = 1 MHz, gains 1 to 128	7
Power supply current (BUF = 1, 1 MHz, gains 1 to 128)	IDD			0.6	mA	VDD = 3 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 1, fCLKIN = 1 MHz, gains 1 to 128	7
Power supply current (BUF = 0, 2.4576 MHz, gains 1 to 4)	IDD			0.4	mA	VDD = 3 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 0, fCLKIN = 2.4576 MHz, gains 1 to 4	7
Power supply current (BUF = 0, 2.4576 MHz, gains 8 to 128)	IDD			0.6	mA	VDD = 3 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 0, fCLKIN = 2.4576 MHz, gains 8 to 128	7
Power supply current (BUF = 1, 2.4576 MHz, gains 1 to 4)	IDD			0.7	mA	VDD = 3 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 1, fCLKIN = 2.4576 MHz, gains 1 to 4	7
Power supply current (BUF = 1, 2.4576 MHz, gains 8 to 128)	IDD			1.1	mA	VDD = 3 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 1, fCLKIN = 2.4576 MHz, gains 8 to 128	7
Power supply current (BUF = 0, 1 MHz, gains 1 to 128)	IDD			0.45	mA	VDD = 5 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 0, fCLKIN = 1 MHz, gains 1 to 128	7
Power supply current (BUF = 1, 1 MHz, gains 1 to 128)	IDD			0.7	mA	VDD = 5 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 1, fCLKIN = 1 MHz, gains 1 to 128	7
Power supply current (BUF = 0, 2.4576 MHz, gains 1 to 4)	IDD			0.6	mA	VDD = 5 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 0, fCLKIN = 2.4576 MHz, gains 1 to 4	7
Power supply current (BUF = 0, 2.4576 MHz, gains 8 to 128)	IDD			0.85	mA	VDD = 5 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 0, fCLKIN = 2.4576 MHz, gains 8 to 128	7
Power supply current (BUF = 1, 2.4576 MHz, gains 1 to 4)	IDD			0.9	mA	VDD = 5 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 1, fCLKIN = 2.4576 MHz, gains 1 to 4	7
Power supply current (BUF = 1, 2.4576 MHz, gains 8 to 128)	IDD			1.3	mA	VDD = 5 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 1, fCLKIN = 2.4576 MHz, gains 8 to 128	7
Standby (power-down) current	IDD			16	μA	VDD = 5 V; external MCLK IN = 0 V or VDD	7
Standby (power-down) current	IDD			8	μA	VDD = 3 V; external MCLK IN = 0 V or VDD	7
VDD to GND	VDD	-0.3		7	V		9
Analog input voltage to GND		-0.3			V	Printed as VDD + 0.3 V; numeric max not applicable	9
Reference input voltage to GND		-0.3			V	Printed as VDD + 0.3 V; numeric max not applicable	9
Digital input voltage to GND		-0.3			V	Printed as VDD + 0.3 V; numeric max not applicable	9
Digital output voltage to GND		-0.3			V	Printed as VDD + 0.3 V; numeric max not applicable	9
Operating temperature range (B version)	TA	-40		85	°C	Commercial (B version)	9
Storage temperature range		-65		150	°C		9
Junction temperature	TJ			150	°C		9
Power dissipation (SSOP/TSSOP package)				450	mW	Package listed as SSOP in datasheet	9
Lead temperature, vapor phase soldering (60 s)				215	°C	SSOP package	9
Lead temperature, infrared soldering (15 s)				220	°C	SSOP package	9
ESD rating		4000			V	Printed as >4000 V	9
Thermal impedance, junction to ambient (θJA)	θJA		139		°C/W	SSOP package; single value printed	9

CAD (KiCad official)

Symbol: AD7705BRUZ-REEL
Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
3D model: TSSOP-16 (KiCad packages3D, STEP)
3D model files: ad7705bruz-reel-etched.step / ad7705bruz-reel-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7705bruz-reel.step / ad7705bruz-reel.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (44 pp, sha256 822cb538aa5c64e3, retrieved 2026-10-20, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# AD7705BRUZ-REEL

**Analog Devices** · Analog To Digital Converters (ADC) · TSSOP-16

AD7705BRUZ-REEL from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCLK | input | Schmitt-triggered serial clock input used to access serial data, which may be a continuous or non-continuous clock. |
| 2 | MCLK IN | input | Master clock input that accepts a crystal/resonator across MCLK IN and MCLK OUT or a CMOS-compatible external clock, with operating clock frequencies from 500 kHz to 5 MHz. |
| 3 | MCLK OUT | output | Provides an inverted clock when an external clock drives MCLK IN, is capable of driving 1 CMOS load, and can be turned off via the CLKDIS bit of the clock register. |
| 4 | CS | input | Active-low chip select input that selects the device; it can be hardwired low for 3-wire interface operation. |
| 5 | RESET | input | Active-low input that resets the control logic, interface logic, calibration coefficients, digital filter and analog modulator to power-on status. |
| 6 | AIN2(+) | input | Positive input of the differential analog input pair AIN2(+)/AIN2(-) on the AD7705. |
| 7 | AIN1(+) | input | Positive input of the differential analog input pair AIN1(+)/AIN1(-) on the AD7705. |
| 8 | AIN1(−) | input | Negative input of the differential analog input pair AIN1(+)/AIN1(-) on the AD7705. |
| 9 | REF IN(+) | input | Positive input of the differential reference input, which must be greater than REF IN(-) and can lie anywhere between VDD and GND. |
| 10 | REF IN(−) | input | Negative input of the differential reference input, which can lie anywhere between VDD and GND provided REF IN(+) is greater than REF IN(-). |
| 11 | AIN2(−) | input | Negative input of the differential analog input pair AIN2(+)/AIN2(-) on the AD7705. |
| 12 | DRDY | output | Logic output that goes low when a new output word is available in the data register, returns high after a full word is read, and also indicates completion of on-chip calibration. |
| 13 | DOUT | output | Serial data output from the output shift register, which can contain setup, communication, clock or data register contents depending on register selection bits. |
| 14 | DIN | input | Serial data input to the input shift register, transferred to the setup, clock or communication register depending on the register selection bits. |
| 15 | VDD | power_in | Supply voltage, 2.7 V to 5.25 V operation. |
| 16 | GND | power_in | Ground reference point for the internal circuitry of the device. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-16 |
| Category | Data Acquisition |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD voltage (3 V operation) | VDD | 2.7 |  | 3.3 | V | For specified performance | 7 |
| VDD voltage (5 V operation) | VDD | 4.75 |  | 5.25 | V | For specified performance | 7 |
| Master clock frequency | fCLKIN | 400 |  |  | kHz | Crystal oscillator or externally supplied | 8 |
| Master clock frequency | fCLKIN |  |  | 2.5 | MHz | For specified performance | 8 |
| Master clock input low time | tCLKIN LO | 0.4 |  |  | × tCLKIN ns | tCLKIN = 1/fCLKIN; printed as 0.4 × tCLKIN ns min | 8 |
| Master clock input high time | tCLKIN HI | 0.4 |  |  | × tCLKIN ns | tCLKIN = 1/fCLKIN; printed as 0.4 × tCLKIN ns min | 8 |
| RESET pulse width | t2 | 100 |  |  | ns |  | 8 |
| DRDY to CS setup time | t3 | 0 |  |  | ns |  | 8 |
| CS falling edge to SCLK rising edge setup time (read) | t4 | 120 |  |  | ns |  | 8 |
| SCLK falling edge to data valid delay | t5 | 0 |  |  | ns |  | 8 |
| SCLK falling edge to data valid delay | t5 |  |  | 80 | ns | VDD = 5 V | 8 |
| SCLK falling edge to data valid delay | t5 |  |  | 100 | ns | VDD = 3.0 V | 8 |
| SCLK high pulse width | t6 | 100 |  |  | ns |  | 8 |
| SCLK low pulse width | t7 | 100 |  |  | ns |  | 8 |
| CS rising edge to SCLK rising edge hold time | t8 | 0 |  |  | ns |  | 8 |
| Bus relinquish time after SCLK rising edge | t9 | 10 |  |  | ns |  | 8 |
| Bus relinquish time after SCLK rising edge | t9 |  |  | 60 | ns | VDD = 5 V | 8 |
| Bus relinquish time after SCLK rising edge | t9 |  |  | 100 | ns | VDD = 3.0 V | 8 |
| SCLK falling edge to DRDY high | t10 |  |  | 100 | ns |  | 8 |
| CS falling edge to SCLK rising edge setup time (write) | t11 | 120 |  |  | ns |  | 8 |
| Data valid to SCLK rising edge setup time | t12 | 30 |  |  | ns |  | 8 |
| Data valid to SCLK rising edge hold time | t13 | 20 |  |  | ns |  | 8 |
| SCLK high pulse width (write) | t14 | 100 |  |  | ns |  | 8 |
| SCLK low pulse width (write) | t15 | 100 |  |  | ns |  | 8 |
| CS rising edge to SCLK rising edge hold time (write) | t16 | 0 |  |  | ns |  | 8 |
| Power supply current (BUF = 0, 1 MHz, gains 1 to 128) | IDD |  |  | 0.32 | mA | VDD = 3 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 0, fCLKIN = 1 MHz, gains 1 to 128 | 7 |
| Power supply current (BUF = 1, 1 MHz, gains 1 to 128) | IDD |  |  | 0.6 | mA | VDD = 3 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 1, fCLKIN = 1 MHz, gains 1 to 128 | 7 |
| Power supply current (BUF = 0, 2.4576 MHz, gains 1 to 4) | IDD |  |  | 0.4 | mA | VDD = 3 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 0, fCLKIN = 2.4576 MHz, gains 1 to 4 | 7 |
| Power supply current (BUF = 0, 2.4576 MHz, gains 8 to 128) | IDD |  |  | 0.6 | mA | VDD = 3 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 0, fCLKIN = 2.4576 MHz, gains 8 to 128 | 7 |
| Power supply current (BUF = 1, 2.4576 MHz, gains 1 to 4) | IDD |  |  | 0.7 | mA | VDD = 3 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 1, fCLKIN = 2.4576 MHz, gains 1 to 4 | 7 |
| Power supply current (BUF = 1, 2.4576 MHz, gains 8 to 128) | IDD |  |  | 1.1 | mA | VDD = 3 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 1, fCLKIN = 2.4576 MHz, gains 8 to 128 | 7 |
| Power supply current (BUF = 0, 1 MHz, gains 1 to 128) | IDD |  |  | 0.45 | mA | VDD = 5 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 0, fCLKIN = 1 MHz, gains 1 to 128 | 7 |
| Power supply current (BUF = 1, 1 MHz, gains 1 to 128) | IDD |  |  | 0.7 | mA | VDD = 5 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 1, fCLKIN = 1 MHz, gains 1 to 128 | 7 |
| Power supply current (BUF = 0, 2.4576 MHz, gains 1 to 4) | IDD |  |  | 0.6 | mA | VDD = 5 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 0, fCLKIN = 2.4576 MHz, gains 1 to 4 | 7 |
| Power supply current (BUF = 0, 2.4576 MHz, gains 8 to 128) | IDD |  |  | 0.85 | mA | VDD = 5 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 0, fCLKIN = 2.4576 MHz, gains 8 to 128 | 7 |
| Power supply current (BUF = 1, 2.4576 MHz, gains 1 to 4) | IDD |  |  | 0.9 | mA | VDD = 5 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 1, fCLKIN = 2.4576 MHz, gains 1 to 4 | 7 |
| Power supply current (BUF = 1, 2.4576 MHz, gains 8 to 128) | IDD |  |  | 1.3 | mA | VDD = 5 V; digital I/Ps = 0 V or VDD, external MCLK IN, CLKDIS = 1; BUF = 1, fCLKIN = 2.4576 MHz, gains 8 to 128 | 7 |
| Standby (power-down) current | IDD |  |  | 16 | μA | VDD = 5 V; external MCLK IN = 0 V or VDD | 7 |
| Standby (power-down) current | IDD |  |  | 8 | μA | VDD = 3 V; external MCLK IN = 0 V or VDD | 7 |
| VDD to GND | VDD | -0.3 |  | 7 | V |  | 9 |
| Analog input voltage to GND |  | -0.3 |  |  | V | Printed as VDD + 0.3 V; numeric max not applicable | 9 |
| Reference input voltage to GND |  | -0.3 |  |  | V | Printed as VDD + 0.3 V; numeric max not applicable | 9 |
| Digital input voltage to GND |  | -0.3 |  |  | V | Printed as VDD + 0.3 V; numeric max not applicable | 9 |
| Digital output voltage to GND |  | -0.3 |  |  | V | Printed as VDD + 0.3 V; numeric max not applicable | 9 |
| Operating temperature range (B version) | TA | -40 |  | 85 | °C | Commercial (B version) | 9 |
| Storage temperature range |  | -65 |  | 150 | °C |  | 9 |
| Junction temperature | TJ |  |  | 150 | °C |  | 9 |
| Power dissipation (SSOP/TSSOP package) |  |  |  | 450 | mW | Package listed as SSOP in datasheet | 9 |
| Lead temperature, vapor phase soldering (60 s) |  |  |  | 215 | °C | SSOP package | 9 |
| Lead temperature, infrared soldering (15 s) |  |  |  | 220 | °C | SSOP package | 9 |
| ESD rating |  | 4000 |  |  | V | Printed as >4000 V | 9 |
| Thermal impedance, junction to ambient (θJA) | θJA |  | 139 |  | °C/W | SSOP package; single value printed | 9 |

## CAD (KiCad official)

- Symbol: `AD7705BRUZ-REEL`
- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`
- 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files: `ad7705bruz-reel-etched.step` / `ad7705bruz-reel-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7705bruz-reel.step` / `ad7705bruz-reel.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588883756014428160) (44 pp, sha256 `822cb538aa5c64e3`, retrieved 2026-10-20, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad7705bruz-reel-datasheet.pdf)