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AD7689ACPZRL7

Analog Devices · Analog To Digital Converters (ADCs) · LFCSP-20(4x4)

AD7689ACPZRL7 from Analog Devices, in a LFCSP-20(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Power supply, nominally 2.5 V to 5.5 V with an external reference, decoupled with 10 µF and 100 nF capacitors; the minimum is 3.0 V when using the internal 2.5 V reference and 4.5 V when using the internal 4.096 V reference.
2 REF bidirectional Reference input/output that produces a selectable 2.5 V or 4.096 V system reference when the internal reference is enabled, or a buffered REFIN voltage up to VDD − 0.5 V, or accepts a precision reference from 0.5 V to VDD; it needs a 10 µF decoupling capacitor placed as close as possible to the pin.
3 REFIN bidirectional Internal unbuffered reference output requiring 0.1 µF decoupling when the internal reference is used, or reference buffer input accepting 0.5 V to (VDD − 0.5 V) when the internal reference buffer is used.
4 GND power_in Power supply ground.
5 GND power_in Power supply ground.
6 IN4 input Analog input channel 4 of the 8-channel multiplexer, with absolute input limits of GND − 0.3 V to VDD + 0.3 V.
7 IN5 input Analog input channel 5 of the 8-channel multiplexer, with absolute input limits of GND − 0.3 V to VDD + 0.3 V.
8 IN6 input Analog input channel 6 of the 8-channel multiplexer, with absolute input limits of GND − 0.3 V to VDD + 0.3 V.
9 IN7 input Analog input channel 7 of the 8-channel multiplexer, with absolute input limits of GND − 0.3 V to VDD + 0.3 V.
10 COM input Common channel input to which all input channels IN[7:0] can be referenced, at a common-mode point of 0 V or VREF/2 V.
11 CNV input Conversion input whose rising edge starts a conversion; holding CNV low during conversion enables the busy indicator.
12 DIN input Data input for writing the 14-bit configuration register, which can be written during and after conversion.
13 SCK input Serial data clock input that clocks data out on SDO and data in on DIN, MSB first.
14 SDO output Serial data output synchronized to SCK, giving straight binary results in unipolar modes and twos complement results in bipolar modes.
15 VIO power_in Input/output interface digital power, nominally at the host interface supply of 1.8 V, 2.5 V, 3 V, or 5 V; VIO to VDD must stay within −0.3 V to VDD + 0.3 V.
16 IN0 input Analog input channel 0, with absolute input limits of GND − 0.3 V to VDD + 0.3 V.
17 IN1 input Analog input channel 1 of the 8-channel multiplexer, with absolute input limits of GND − 0.3 V to VDD + 0.3 V.
18 IN2 input Analog input channel 2 of the 8-channel multiplexer, with absolute input limits of GND − 0.3 V to VDD + 0.3 V.
19 IN3 input Analog input channel 3 of the 8-channel multiplexer, with absolute input limits of GND − 0.3 V to VDD + 0.3 V.
20 VDD power_in Power supply, nominally 2.5 V to 5.5 V with an external reference, decoupled with 10 µF and 100 nF capacitors; the minimum is 3.0 V when using the internal 2.5 V reference and 4.5 V when using the internal 4.096 V reference.
21 EPAD passive Exposed pad that is not connected internally and should be soldered to the system ground plane for increased solder joint reliability.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-20(4x4)
Category ADC/DAC/Data Conversion
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Unipolar analog input voltage range (min) 0 V Unipolar mode; max printed as +VREF 3
Absolute input voltage, positive input (min) -0.1 V Positive input, unipolar and bipolar modes; max printed as VREF + 0.1 3
Absolute input voltage, negative or COM input (unipolar) -0.1 0.1 V Negative or COM input, unipolar mode 3
Conversion rate, full bandwidth 0 250 kSPS VDD = 4.5 V to 5.5 V 3
Conversion rate, full bandwidth 0 200 kSPS VDD = 2.3 V to 4.5 V 3
Conversion rate, 1/4 bandwidth 0 62.5 kSPS VDD = 4.5 V to 5.5 V 3
Conversion rate, 1/4 bandwidth 0 50 kSPS VDD = 2.3 V to 4.5 V 3
Integral linearity error INL -4 4 LSB 3
Differential linearity error DNL -1 1.5 LSB 3
Gain error -32 32 LSB 3
Gain error match -2 2 LSB 3
Gain error temperature drift -1 1 ppm/°C 3
Offset error -32 32 LSB VDD = 4.5 V to 5.5 V 3
Offset error match -2 2 LSB 3
Offset error temperature drift -1 1 ppm/°C 3
Power supply sensitivity -1.5 1.5 LSB VDD = 5 V ± 5% 3
Dynamic range 90.5 93.8 dB 3
Signal-to-noise ratio (SNR) SNR 90 92.5 93.5 dB LFCSP, fIN = 20 kHz, VREF = 5 V 3
Signal-to-noise ratio (SNR) SNR 89 91 92.3 dB fIN = 20 kHz, VREF = 4.096 V, internal REF 3
Signal-to-noise ratio (SNR) SNR 86 87.5 88.8 dB fIN = 20 kHz, VREF = 2.5 V, internal REF 3
Supply voltage VDD (Table 2 conditions) VDD 2.3 5.5 V VIO = 1.8 V to VDD, VREF = VDD, all specifications 3
Interface supply VIO VIO 1.8 V VIO = 1.8 V to VDD; max = VDD 3
Operating ambient temperature TA -40 85 °C Specified range, all specifications unless otherwise noted 3
VDD minimum with internal 2.5 V reference VDD 3 V Internal reference set to 2.5 V output 11
VDD minimum with internal 4.096 V reference VDD 4.5 V Internal reference set to 4.096 V output 11
REF input from precision reference REF 0.5 V Precision reference connected to REF; max = VDD 11
REFIN source for buffered reference REFIN 0.5 V Source buffered to REF; max = VDD − 0.5 V 11
VDD, VIO to GND VDD, VIO -0.3 7 V 10
VIO to VDD VIO -0.3 V Max printed as VDD + 0.3 V 10
DIN, CNV, SCK to GND -0.3 V Max printed as VIO + 0.3 V 10
SDO to GND -0.3 V Max printed as VIO + 0.3 V 10
INx, COM to GND -0.3 V Max printed as VDD + 0.3 V or VDD 10
Analog input current (INx, COM) -130 130 mA 10
REF, REFIN to GND -0.3 V Max printed as VDD + 0.3 V 10
Storage temperature range -65 150 °C 10
Junction temperature TJ 150 °C 10
Thermal impedance, junction-to-ambient (LFCSP) θJA 48 °C/W LFCSP 10
Thermal impedance, junction-to-case (LFCSP) θJC 4.4 °C/W LFCSP 10

CAD (KiCad official)

  • Symbol: AD7689ACPZRL7
  • Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
  • 3D model: LFCSP-20(4x4) (KiCad packages3D, STEP)
  • 3D model files: ad7689acpzrl7-etched.step / ad7689acpzrl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7689acpzrl7.step / ad7689acpzrl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (37 pp, sha256 028312fc80ae8a4b, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF