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AD7685BRMZRL7

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Analog Devices Analog To Digital Converters (ADC), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD7685BRMZRL7

Analog Devices · Analog To Digital Converters (ADC) · MSOP-10

AD7685BRMZRL7 from Analog Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 REF input Reference input voltage with a range from 0.5 V to VDD, referred to GND, and it should be decoupled closely to the pin with a 10 µF capacitor.
2 VDD power_in Power supply, operating from 2.3 V to 5.5 V as specified for the single-supply operation.
3 IN+ input Analog input referred to IN−, where the voltage range (IN+ minus IN−) is 0 V to VREF.
4 IN− input Analog input ground sense, to be connected to the analog ground plane or to a remote sense ground.
5 GND power_in Power supply ground, the reference for REF and the digital and analog pins.
6 CNV input Convert input whose leading edge initiates conversions and selects chain or CS interface mode; in CS mode it enables SDO when low, and in chain mode the data is read while CNV is high.
7 SDO output Serial data output on which the conversion result is output, synchronized to SCK.
8 SCK input Serial data clock input that shifts the conversion result out of the part when it is selected.
9 SDI input Serial data input that selects the interface mode at the CNV rising edge: chain mode if SDI is low (daisy-chain data input, output on SDO after 16 SCK cycles) and CS mode if SDI is high (BUSY indicator enabled if SDI or CNV is low at conversion end).
10 VIO power_in Input/output interface digital power, nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package MSOP-10
Category Data Acquisition
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Integral Linearity Error (B Grade) -3 1 3 LSB 3
Differential Linearity Error (B Grade) -1 0.5 1.5 LSB 3
Gain Error (B Grade), typ ±2 printed, max ±30 printed -30 2 30 LSB TMIN to TMAX 3
Offset Error (B Grade) -1.6 0.1 1.6 mV VDD = 4.5 V to 5.5 V, TMIN to TMAX 3
Offset Error (B Grade) -3.5 0.7 3.5 mV VDD = 2.3 V to 4.5 V, TMIN to TMAX 3
Conversion Rate (B Grade) 0 250 kSPS VDD = 4.5 V to 5.5 V 3
Conversion Rate (B Grade) 0 200 kSPS VDD = 2.3 V to 4.5 V 3
Voltage Range IN+ − IN− (B Grade) 0 V IN+ − IN−; max printed as VREF 3
Absolute Input Voltage IN+ (B Grade) -0.1 V max printed as VDD + 0.1 3
Absolute Input Voltage IN− (B Grade) -0.1 0.1 V 3
Analog Input CMRR (B Grade) 65 dB fIN = 250 kHz 3
Leakage Current at 25°C (B Grade) 1 nA Acquisition phase 3
No Missing Codes (B Grade) 16 Bits 3
Transient Response (B Grade) 1.8 µs Full-scale step 3
Conversion Time: CNV Rising Edge to Data Available tCONV 0.7 3.2 µs VDD = 2.3 V to 4.5 V, −40°C to +85°C 6
Acquisition Time tACQ 1.8 µs VDD = 2.3 V to 4.5 V 6
Time Between Conversions tCYC 5 µs VDD = 2.3 V to 4.5 V 6
CNV Pulse Width (CS Mode) tCNVH 10 ns VDD = 2.3 V to 4.5 V 6
SCK Period (CS Mode) tSCK 25 ns VDD = 2.3 V to 4.5 V 6
SCK Low Time tSCKL 12 ns VDD = 2.3 V to 4.5 V 6
SCK High Time tSCKH 12 ns VDD = 2.3 V to 4.5 V 6
SCK Falling Edge to Data Remains Valid tHSDO 5 ns VDD = 2.3 V to 4.5 V 6
SCK Falling Edge to Data Valid Delay tDSDO 24 ns VIO above 3 V, VDD = 2.3 V to 4.5 V 6
SCK Falling Edge to Data Valid Delay tDSDO 30 ns VIO above 2.7 V, VDD = 2.3 V to 4.5 V 6
SCK Falling Edge to Data Valid Delay tDSDO 35 ns VIO above 2.3 V, VDD = 2.3 V to 4.5 V 6
CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN 18 ns VIO above 2.7 V, VDD = 2.3 V to 4.5 V 6
CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN 22 ns VIO above 2.3 V, VDD = 2.3 V to 4.5 V 6
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 25 ns VDD = 2.3 V to 4.5 V 6
SDI Valid Setup Time from CNV Rising Edge (CS Mode) tSSDICNV 30 ns VDD = 2.3 V to 4.5 V 6
SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 0 ns VDD = 2.3 V to 4.5 V 6
SCK Period (Chain Mode) tSCK 29 ns VIO above 3 V, VDD = 2.3 V to 4.5 V 6
SCK Period (Chain Mode) tSCK 35 ns VIO above 2.7 V, VDD = 2.3 V to 4.5 V 6
SCK Period (Chain Mode) tSCK 40 ns VIO above 2.3 V, VDD = 2.3 V to 4.5 V 6
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns VDD = 2.3 V to 4.5 V 6
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 8 ns VDD = 2.3 V to 4.5 V 6
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 5 ns VDD = 2.3 V to 4.5 V 6
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 4 ns VDD = 2.3 V to 4.5 V 6
Gain Error Temperature Drift (B Grade), printed ±0.3 -0.3 0.3 ppm/°C 3
Offset Temperature Drift (B Grade), printed ±0.3 -0.3 0.3 ppm/°C 3
Supply Voltage VDD VDD 2.3 5.5 V 16
Interface Supply VIO VIO 2.3 V max printed as VDD 3
Operating Temperature Range TA -40 85 °C 3
Reference Input Voltage REF REF 0.5 V max printed as VDD; referred to GND 8
Supply Voltages VDD, VIO to GND -0.3 7 V 7
VDD to VIO -7 7 V ±7 V printed 7
Digital Inputs to GND -0.3 V max printed as VIO + 0.3 V 7
Digital Outputs to GND -0.3 V max printed as VIO + 0.3 V 7
Analog Inputs IN+, IN−, REF to GND -0.3 V max printed as VDD + 0.3 V, or ±130 mA 7
Analog Input Diode Forward Current -130 130 mA printed ±130 mA 7
Storage Temperature Range -65 150 °C 7
Junction Temperature 150 °C 7
Lead Temperature, Vapor Phase 215 °C 60 sec 7
Lead Temperature, Infrared 220 °C 15 sec 7
Thermal Impedance θJA (MSOP-10) θJA 200 °C/W 7
Thermal Impedance θJC (MSOP-10) θJC 44 °C/W 7
Transition Noise (B Grade) 0.5 LSB REF = VDD = 5 V 3
Resolution 16 Bits 3
Power Supply Sensitivity (B Grade) 0.05 LSB VDD = 5 V ± 5% 3

CAD (KiCad official)

  • Symbol: AD7685BRMZRL7
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: ad7685brmzrl7-etched.step / ad7685brmzrl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7685brmzrl7.step / ad7685brmzrl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (28 pp, sha256 c66bc54d5dd6d97a, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF