component
AD7680BRMZ-REEL7
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADCs), MSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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AD7680BRMZ-REEL7
Analog Devices · Analog To Digital Converters (ADCs) · MSOP-8
AD7680BRMZ-REEL7 from Analog Devices, in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Power supply input; the VDD range for the AD7680 is 2.5 V to 5.5 V. |
| 2 | GND | power_in | Analog ground and ground reference point for all circuitry on the AD7680; all analog input signals should be referred to this GND voltage. |
| 3 | GND | power_in | Analog ground and ground reference point for all circuitry on the AD7680; all analog input signals should be referred to this GND voltage. |
| 4 | VIN | power_in | Single-ended analog input channel; the input range is 0 V to VDD. |
| 5 | SCLK | input | Serial clock logic input that provides the serial clock for accessing data and is also the clock source for the conversion process. |
| 6 | NC | unconnected | No connect; this pin should be left unconnected. |
| 7 | SDATA | output | Data out logic output that provides the conversion result as a serial stream clocked out on the falling edge of SCLK, consisting of four leading zeros followed by 16 data bits MSB first. |
| 8 | CS | input | Active-low chip select logic input that initiates conversions and frames the serial data transfer. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | MSOP-8 |
| Category | Data Converters |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Signal-to-Noise + Distortion (SINAD) | 83 | dB | fIN = 10 kHz sine wave | 3 | |||
| Signal-to-Noise Ratio (SNR) | 84 | dB | fIN = 10 kHz sine wave | 3 | |||
| Aperture Delay | 20 | ns | 3 | ||||
| Offset Error | -1.68 | 1.68 | mV | 3 | |||
| Gain Error | -0.038 | 0.038 | % FS | 3 | |||
| DC Leakage Current | -0.3 | 0.3 | μA | 3 | |||
| Input High Voltage | VINH | 2.8 | V | 3 | |||
| Input Low Voltage | VINL | 0.4 | V | 3 | |||
| Input Current | IIN | -0.3 | 0.3 | μA | Typically 10 nA, VIN = 0 V or VDD | 3 | |
| Input Capacitance | CIN | 10 | pF | 3 | |||
| Output Low Voltage | VOL | 0.4 | V | ISINK = 200 μA | 3 | ||
| Floating-State Leakage Current | -0.3 | 0.3 | μA | 3 | |||
| Floating-State Output Capacitance | 10 | pF | 3 | ||||
| Conversion Time | 8 | μs | 20 SCLK cycles with SCLK at 2.5 MHz | 3 | |||
| Conversion Time | 9.6 | μs | 24 SCLK cycles with SCLK at 2.5 MHz | 3 | |||
| Track-and-Hold Acquisition Time | 1.5 | μs | 3 | ||||
| Track-and-Hold Acquisition Time | 400 | ns | Sine wave input ≤ 10 kHz | 3 | |||
| Supply Voltage VDD | VDD | 4.5 | 5.5 | V | 3 | ||
| Normal Mode (Static) supply current | IDD | 5.2 | mA | SCLK on or off. VDD = 5.5 V | 3 | ||
| Normal Mode (Operational) supply current | IDD | 3.3 | 4.8 | mA | fSAMPLE = 100 kSPS. VDD = 5.5 V | 3 | |
| Full Power-Down Mode supply current | IDD | 0.5 | μA | SCLK on or off. VDD = 5.5 V | 3 | ||
| Power Dissipation Normal Mode (Operational) | 26.4 | mW | VDD = 5.5 V; fSAMPLE = 100 kSPS | 3 | |||
| Power Dissipation Full Power-Down | 2.75 | μW | VDD = 5.5 V | 3 | |||
| Supply Voltage VDD | VDD | 2.5 | 4.096 | V | 5 | ||
| Normal Mode (Static) supply current | IDD | 2.8 | mA | SCLK on or off; VDD = 4.096 V | 5 | ||
| Normal Mode (Static) supply current | IDD | 2 | mA | SCLK on or off; VDD = 3.6 V | 5 | ||
| Normal Mode (Operational) supply current | IDD | 1.75 | 2.6 | mA | fSAMPLE = 100 kSPS; VDD = 4.096 V | 5 | |
| Normal Mode (Operational) supply current | IDD | 1.29 | 1.9 | mA | fSAMPLE = 100 kSPS; VDD = 3.6 V | 5 | |
| Full Power-Down Mode supply current | IDD | 0.3 | μA | SCLK on or off | 5 | ||
| Power Dissipation Normal Mode (Operational) | 10.65 | mW | fSAMPLE = 100 kSPS; VDD = 4.096 V | 5 | |||
| Power Dissipation Normal Mode (Operational) | 6.84 | mW | fSAMPLE = 100 kSPS; VDD = 3.6 V | 5 | |||
| Power Dissipation Full Power-Down | 1.23 | μW | VDD = 4.096V | 5 | |||
| Power Dissipation Full Power-Down | 1.08 | μW | VDD = 3.6 V | 5 | |||
| fSCLK minimum | fSCLK | 250 | kHz | 3 V and 5 V columns | 6 | ||
| fSCLK maximum | fSCLK | 2.5 | MHz | 3 V and 5 V columns | 6 | ||
| Conversion time | tCONVERT | 20 | × tSCLK | 3 V and 5 V columns | 6 | ||
| Quiet time | tQUIET | 100 | ns | Minimum quiet time between bus relinquish and start of next conversion; 3 V and 5 V columns | 6 | ||
| CS pulse width | t1 | 10 | ns | Minimum CS pulse width; 3 V and 5 V columns | 6 | ||
| CS to SCLK setup time | t2 | 10 | ns | 3 V and 5 V columns | 6 | ||
| Delay from CS until SDATA three-state disabled | t3 | 48 | ns | 3 V column | 6 | ||
| Delay from CS until SDATA three-state disabled | t3 | 35 | ns | 5 V column | 6 | ||
| Data access time after SCLK falling edge | t4 | 120 | ns | 3 V column | 6 | ||
| Data access time after SCLK falling edge | t4 | 80 | ns | 5 V column | 6 | ||
| SCLK low pulse width | t5 | 0.4 | tSCLK | 3 V and 5 V columns | 6 | ||
| SCLK high pulse width | t6 | 0.4 | tSCLK | 3 V and 5 V columns | 6 | ||
| SCLK to data valid hold time | t7 | 10 | ns | 3 V and 5 V columns | 6 | ||
| SCLK falling edge to SDATA high impedance | t8 | 45 | ns | 3 V column | 6 | ||
| SCLK falling edge to SDATA high impedance | t8 | 35 | ns | 5 V column | 6 | ||
| VDD to GND | VDD | -0.3 | 7 | V | TA = 25°C | 7 | |
| Analog Input Voltage to GND | -0.3 | V | Upper limit VDD + 0.3 V (not numeric) | 7 | |||
| Digital Input Voltage to GND | -0.3 | 7 | V | TA = 25°C | 7 | ||
| Digital Output Voltage to GND | -0.3 | V | Upper limit VDD + 0.3 V (not numeric) | 7 | |||
| Input Current to Any Pin Except Supplies | -10 | 10 | mA | 7 | |||
| Operating Temperature Range (Commercial, B Version) | -40 | 85 | °C | B Version | 7 | ||
| Storage Temperature Range | -65 | 150 | °C | 7 | |||
| Junction Temperature | 150 | °C | 7 | ||||
| Power Dissipation (MSOP package) | 450 | mW | MSOP package | 7 | |||
| ESD rating | 2 | kV | 7 | ||||
| Thermal impedance junction-to-ambient (MSOP) | θJA | 205.9 | °C/W | MSOP package | 7 | ||
| Thermal impedance junction-to-case (MSOP) | θJC | 43.74 | °C/W | MSOP package | 7 |
CAD (KiCad official)
- Symbol:
AD7680BRMZ-REEL7 - Footprint:
Package_SO:MSOP-8_3x3mm_P0.65mm - 3D model: MSOP-8 (KiCad packages3D, STEP)
- 3D model files:
ad7680brmz-reel7-etched.step/ad7680brmz-reel7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7680brmz-reel7.step/ad7680brmz-reel7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (24 pp, sha256
e670fa089e166d3e, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).