component
AD7663ASTZRL
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADCs), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"title": "AD7663ASTZRL",
"brief": "Analog Devices Analog To Digital Converters (ADCs), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
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"mpn": "AD7663ASTZRL",
"manufacturer": "Analog Devices",
"package": "LQFP-48(7x7)",
"pin_count": 48,
"category": "Data Converters",
"subcategory": "Analog To Digital Converters (ADCs)",
"datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD7663.pdf",
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"distributor_links": {
"lcsc": "C16724",
"digikey": "505-AD7663ASTZRLTR-ND",
"mouser": "584-AD7663ASTZR"
},
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"checked_at": "2026-10-30T22:42:19Z",
"source": "Component Ocean /api/assign-pns",
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"pn": "505-AD7663ASTZRLTR-ND",
"status": "found"
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"pins": [
{
"number": "1",
"name": "AGND",
"type": "power_in",
"description": "Analog power ground pin that must be tied to analog ground."
},
{
"number": "2",
"name": "AVDD",
"type": "power_in",
"description": "Analog input power pin, nominally 5 V."
},
{
"number": "3",
"name": "NC",
"type": "unconnected",
"description": "No connect."
},
{
"number": "4",
"name": "BYTESWAP",
"type": "input",
"description": "Parallel mode byte selection: when LOW the LSB is output on D[7:0] and the MSB on D[15:8]; when HIGH the positions are swapped."
},
{
"number": "5",
"name": "OB/2C",
"type": "input",
"description": "Output coding select: HIGH gives straight binary output, LOW inverts the MSB to give twos complement output."
},
{
"number": "6",
"name": "NC",
"type": "unconnected",
"description": "No connect."
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{
"number": "7",
"name": "NC",
"type": "unconnected",
"description": "No connect."
},
{
"number": "8",
"name": "SER/PAR",
"type": "input",
"description": "Interface select: LOW selects the parallel port and HIGH selects the serial interface mode."
},
{
"number": "9",
"name": "D0",
"type": "output",
"description": "Bit 0 of the parallel port data output bus; high impedance when SER/PAR is HIGH."
},
{
"number": "10",
"name": "D1",
"type": "output",
"description": "Bit 1 of the parallel port data output bus; high impedance when SER/PAR is HIGH."
},
{
"number": "11",
"name": "D2/DIVSCLK[0]",
"type": "bidirectional",
"description": "Parallel data bit 2 when SER/PAR is LOW; serial master read after convert clock divider input DIVSCLK[0] when SER/PAR is HIGH."
},
{
"number": "12",
"name": "D3/DIVSCLK[1]",
"type": "bidirectional",
"description": "Parallel data bit 3 when SER/PAR is LOW; serial master read after convert clock divider input DIVSCLK[1] when SER/PAR is HIGH."
},
{
"number": "13",
"name": "D4/EXT/INT",
"type": "bidirectional",
"description": "Parallel data bit 4 when SER/PAR is LOW; internal or external serial clock select (Master/Slave) when SER/PAR is HIGH."
},
{
"number": "14",
"name": "D5/INVSYNC",
"type": "bidirectional",
"description": "Parallel data bit 5 when SER/PAR is LOW; selects the active state of SYNC when SER/PAR is HIGH."
},
{
"number": "15",
"name": "D6/INVSCLK",
"type": "bidirectional",
"description": "Parallel data bit 6 when SER/PAR is LOW; inverts the SCLK signal in serial modes when SER/PAR is HIGH."
},
{
"number": "16",
"name": "D7/RDC/SDIN",
"type": "bidirectional",
"description": "Parallel data bit 7 when SER/PAR is LOW; external serial data input or read mode select when SER/PAR is HIGH."
},
{
"number": "17",
"name": "OGND",
"type": "power_in",
"description": "Input/output interface digital power ground."
},
{
"number": "18",
"name": "OVDD",
"type": "power_in",
"description": "Input/output interface digital power, nominally at the host interface supply of 5 V or 3 V."
},
{
"number": "19",
"name": "DVDD",
"type": "power_in",
"description": "Digital power, nominally 5 V."
},
{
"number": "20",
"name": "DGND",
"type": "power_in",
"description": "Digital power ground."
},
{
"number": "21",
"name": "D8/SDOUT",
"type": "output",
"description": "Parallel data bit 8 when SER/PAR is LOW; serial data output synchronized to SCLK when SER/PAR is HIGH."
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{
"number": "22",
"name": "D9/SCLK",
"type": "bidirectional",
"description": "Parallel data bit 9 when SER/PAR is LOW; serial data clock input or output when SER/PAR is HIGH."
},
{
"number": "23",
"name": "D10/SYNC",
"type": "output",
"description": "Parallel data bit 10 when SER/PAR is LOW; digital frame synchronization output for the internal data clock when SER/PAR is HIGH."
},
{
"number": "24",
"name": "D11/RDERROR",
"type": "output",
"description": "Parallel data bit 11 when SER/PAR is LOW; incomplete read error flag in serial master mode when SER/PAR and EXT/INT are HIGH."
},
{
"number": "25",
"name": "D12",
"type": "output",
"description": "Bit 12 of the parallel port data output bus; high impedance when SER/PAR is HIGH."
},
{
"number": "26",
"name": "D13",
"type": "output",
"description": "Bit 13 of the parallel port data output bus; high impedance when SER/PAR is HIGH."
},
{
"number": "27",
"name": "D14",
"type": "output",
"description": "Bit 14 of the parallel port data output bus; high impedance when SER/PAR is HIGH."
},
{
"number": "28",
"name": "D15",
"type": "output",
"description": "Bit 15 of the parallel port data output bus; high impedance when SER/PAR is HIGH."
},
{
"number": "29",
"name": "BUSY",
"type": "output",
"description": "Busy output that goes HIGH when a conversion starts and stays HIGH until the result is latched; its falling edge can serve as a data-ready clock."
},
{
"number": "30",
"name": "DGND",
"type": "power_in",
"description": "Must be tied to digital ground."
},
{
"number": "31",
"name": "RD",
"type": "input",
"description": "Read data input; with CS LOW, enables the parallel or serial output bus when RD is also LOW."
},
{
"number": "32",
"name": "CS",
"type": "input",
"description": "Chip select; with RD LOW, enables the output bus, and it also gates the external clock."
},
{
"number": "33",
"name": "RESET",
"type": "input",
"description": "Reset input: HIGH resets the AD7663 and aborts any current conversion; if unused it may be tied to DGND."
},
{
"number": "34",
"name": "PD",
"type": "input",
"description": "Power-down input: HIGH reduces power consumption and inhibits conversions after the current one completes."
},
{
"number": "35",
"name": "CNVST",
"type": "input",
"description": "Start conversion input; the falling edge starts a conversion, with timing depending on whether CNVST is HIGH or LOW when the acquisition phase completes."
},
{
"number": "36",
"name": "AGND",
"type": "power_in",
"description": "Must be tied to analog ground."
},
{
"number": "37",
"name": "REF",
"type": "passive",
"description": "Reference input voltage."
},
{
"number": "38",
"name": "REFGND",
"type": "power_in",
"description": "Reference input analog ground, which senses the reference and must be a low impedance return."
},
{
"number": "39",
"name": "INGND",
"type": "power_in",
"description": "Analog input ground used to sense the analog input signal."
},
{
"number": "40",
"name": "INA",
"type": "passive",
"description": "Analog input A; refer to Table I for the input range configuration."
},
{
"number": "41",
"name": "INB",
"type": "passive",
"description": "Analog input B; refer to Table I for the input range configuration."
},
{
"number": "42",
"name": "INC",
"type": "passive",
"description": "Analog input C; refer to Table I for the input range configuration."
},
{
"number": "43",
"name": "IND",
"type": "passive",
"description": "Analog input D; refer to Table I for the input range configuration."
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{
"number": "44",
"name": "NC",
"type": "unconnected",
"description": "No connect."
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{
"number": "45",
"name": "NC",
"type": "unconnected",
"description": "No connect."
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{
"number": "46",
"name": "NC",
"type": "unconnected",
"description": "No connect."
},
{
"number": "47",
"name": "NC",
"type": "unconnected",
"description": "No connect."
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{
"number": "48",
"name": "NC",
"type": "unconnected",
"description": "No connect."
}
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