# AD7663ASTZRL

**Analog Devices** · Analog To Digital Converters (ADCs) · LQFP-48(7x7)

AD7663ASTZRL from Analog Devices, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AGND | power_in | Analog power ground pin that must be tied to analog ground. |
| 2 | AVDD | power_in | Analog input power pin, nominally 5 V. |
| 3 | NC | unconnected | No connect. |
| 4 | BYTESWAP | input | Parallel mode byte selection: when LOW the LSB is output on D[7:0] and the MSB on D[15:8]; when HIGH the positions are swapped. |
| 5 | OB/2C | input | Output coding select: HIGH gives straight binary output, LOW inverts the MSB to give twos complement output. |
| 6 | NC | unconnected | No connect. |
| 7 | NC | unconnected | No connect. |
| 8 | SER/PAR | input | Interface select: LOW selects the parallel port and HIGH selects the serial interface mode. |
| 9 | D0 | output | Bit 0 of the parallel port data output bus; high impedance when SER/PAR is HIGH. |
| 10 | D1 | output | Bit 1 of the parallel port data output bus; high impedance when SER/PAR is HIGH. |
| 11 | D2/DIVSCLK[0] | bidirectional | Parallel data bit 2 when SER/PAR is LOW; serial master read after convert clock divider input DIVSCLK[0] when SER/PAR is HIGH. |
| 12 | D3/DIVSCLK[1] | bidirectional | Parallel data bit 3 when SER/PAR is LOW; serial master read after convert clock divider input DIVSCLK[1] when SER/PAR is HIGH. |
| 13 | D4/EXT/INT | bidirectional | Parallel data bit 4 when SER/PAR is LOW; internal or external serial clock select (Master/Slave) when SER/PAR is HIGH. |
| 14 | D5/INVSYNC | bidirectional | Parallel data bit 5 when SER/PAR is LOW; selects the active state of SYNC when SER/PAR is HIGH. |
| 15 | D6/INVSCLK | bidirectional | Parallel data bit 6 when SER/PAR is LOW; inverts the SCLK signal in serial modes when SER/PAR is HIGH. |
| 16 | D7/RDC/SDIN | bidirectional | Parallel data bit 7 when SER/PAR is LOW; external serial data input or read mode select when SER/PAR is HIGH. |
| 17 | OGND | power_in | Input/output interface digital power ground. |
| 18 | OVDD | power_in | Input/output interface digital power, nominally at the host interface supply of 5 V or 3 V. |
| 19 | DVDD | power_in | Digital power, nominally 5 V. |
| 20 | DGND | power_in | Digital power ground. |
| 21 | D8/SDOUT | output | Parallel data bit 8 when SER/PAR is LOW; serial data output synchronized to SCLK when SER/PAR is HIGH. |
| 22 | D9/SCLK | bidirectional | Parallel data bit 9 when SER/PAR is LOW; serial data clock input or output when SER/PAR is HIGH. |
| 23 | D10/SYNC | output | Parallel data bit 10 when SER/PAR is LOW; digital frame synchronization output for the internal data clock when SER/PAR is HIGH. |
| 24 | D11/RDERROR | output | Parallel data bit 11 when SER/PAR is LOW; incomplete read error flag in serial master mode when SER/PAR and EXT/INT are HIGH. |
| 25 | D12 | output | Bit 12 of the parallel port data output bus; high impedance when SER/PAR is HIGH. |
| 26 | D13 | output | Bit 13 of the parallel port data output bus; high impedance when SER/PAR is HIGH. |
| 27 | D14 | output | Bit 14 of the parallel port data output bus; high impedance when SER/PAR is HIGH. |
| 28 | D15 | output | Bit 15 of the parallel port data output bus; high impedance when SER/PAR is HIGH. |
| 29 | BUSY | output | Busy output that goes HIGH when a conversion starts and stays HIGH until the result is latched; its falling edge can serve as a data-ready clock. |
| 30 | DGND | power_in | Must be tied to digital ground. |
| 31 | RD | input | Read data input; with CS LOW, enables the parallel or serial output bus when RD is also LOW. |
| 32 | CS | input | Chip select; with RD LOW, enables the output bus, and it also gates the external clock. |
| 33 | RESET | input | Reset input: HIGH resets the AD7663 and aborts any current conversion; if unused it may be tied to DGND. |
| 34 | PD | input | Power-down input: HIGH reduces power consumption and inhibits conversions after the current one completes. |
| 35 | CNVST | input | Start conversion input; the falling edge starts a conversion, with timing depending on whether CNVST is HIGH or LOW when the acquisition phase completes. |
| 36 | AGND | power_in | Must be tied to analog ground. |
| 37 | REF | passive | Reference input voltage. |
| 38 | REFGND | power_in | Reference input analog ground, which senses the reference and must be a low impedance return. |
| 39 | INGND | power_in | Analog input ground used to sense the analog input signal. |
| 40 | INA | passive | Analog input A; refer to Table I for the input range configuration. |
| 41 | INB | passive | Analog input B; refer to Table I for the input range configuration. |
| 42 | INC | passive | Analog input C; refer to Table I for the input range configuration. |
| 43 | IND | passive | Analog input D; refer to Table I for the input range configuration. |
| 44 | NC | unconnected | No connect. |
| 45 | NC | unconnected | No connect. |
| 46 | NC | unconnected | No connect. |
| 47 | NC | unconnected | No connect. |
| 48 | NC | unconnected | No connect. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LQFP-48(7x7) |
| Category | Data Converters |
| Pins | 48 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltages AVDD, DVDD, OVDD |  | -0.3 |  | 7 | V | AVDD, DVDD, OVDD to ground | 5 |
| Analog inputs IND, INC, INB |  | -11 |  | 30 | V |  | 5 |
| Ground voltage differences AGND, DGND, OGND |  | -0.3 |  | 0.3 | V |  | 5 |
| AVDD to DVDD and AVDD to OVDD |  | -7 |  | 7 | V |  | 5 |
| DVDD to OVDD |  | -0.3 |  | 7 | V |  | 5 |
| Analog inputs INA, REF, INGND, REFGND |  | -0.3 |  |  | V | Referenced to AGND: min AGND - 0.3 V, max AVDD + 0.3 V | 5 |
| Digital inputs |  | -0.3 |  |  | V | Referenced to DVDD: max DVDD + 0.3 V | 5 |
| Internal power dissipation (LQFP) |  |  |  | 700 | mW | Free air, 48-Lead LQFP | 5 |
| Internal power dissipation (LFCSP) |  |  |  | 2.5 | W | Free air, 48-Lead LFCSP | 5 |
| Junction temperature |  |  |  | 150 | °C |  | 5 |
| Storage temperature range |  | -65 |  | 150 | °C |  | 5 |
| Lead temperature range |  |  |  | 300 | °C | Soldering 10 sec | 5 |
| Thermal resistance junction-to-ambient | θJA |  | 91 |  | °C/W | Free air, 48-Lead LQFP | 5 |
| Thermal resistance junction-to-case | θJC |  | 30 |  | °C/W | Free air, 48-Lead LQFP | 5 |
| Thermal resistance junction-to-case | θJC |  | 26 |  | °C/W | Free air, 48-Lead LFCSP | 5 |
| External SCLK active edge to SDOUT delay | t32 | 3 |  | 16 | ns | Slave serial interface modes | 4 |

## CAD (KiCad official)

- Symbol: `AD7663ASTZRL`
- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`
- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `ad7663astzrl-etched.step` / `ad7663astzrl-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7663astzrl.step` / `ad7663astzrl.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7663.pdf) (24 pp, sha256 `7c94e5d758caa492`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad7663astzrl-datasheet.pdf)