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AD7663ASTZ

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Analog Devices Analog To Digital Converters (ADCs), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Verified AD7663ASTZ

by Ray · last 2 Nov 2026 · 1 record · files match
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Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 48 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD7663ASTZ · LQFP-48(7x7) · 48 pins
  • ✓copper: 48 copper pads, none touching another net
  • ✓datasheet: all 48 pin names found in the 24-page datasheet
  • ✓distributor: lcsc C495031, digikey 505-AD7663ASTZ-ND, mouser 584-AD7663ASTZ
  • ✓family: LQFP-48_7x7mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-vqwks1fj/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 48 pins = 48 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 48 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad7663astz.kicad_sym✓ ad7663astz.kicad_mod✓ ad7663astz.step
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AD7663ASTZ

Analog Devices · Analog To Digital Converters (ADCs) · LQFP-48(7x7)

AD7663ASTZ from Analog Devices, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AGND power_in Analog power ground pin that must be tied to analog ground.
2 AVDD power_in Input analog power pin, nominally 5 V.
3 NC unconnected No connect.
4 BYTESWAP input Parallel mode byte selection: when LOW the LSB is output on D[7:0], when HIGH the LSB is output on D[15:8].
5 OB/2C input Output format select: when HIGH the output is straight binary, when LOW the MSB is inverted for twos complement output.
6 NC unconnected No connect.
7 NC unconnected No connect.
8 SER/PAR input Serial/parallel selection: when LOW the parallel port is selected, when HIGH the serial interface mode is selected.
9 D0 output Bit 0 of the parallel port data output bus, high impedance when SER/PAR is HIGH.
10 D1 output Bit 1 of the parallel port data output bus, high impedance when SER/PAR is HIGH.
11 D2/DIVSCLK[0] bidirectional Parallel data bit 2 when SER/PAR is LOW; DIVSCLK[0] serial clock slow-down input in Serial Master Read after Convert mode.
12 D3/DIVSCLK[1] bidirectional Parallel data bit 3 when SER/PAR is LOW; DIVSCLK[1] serial clock slow-down input in Serial Master Read after Convert mode.
13 D4/EXT/INT bidirectional Parallel data bit 4 when SER/PAR is LOW; when SER/PAR is HIGH it selects internal (LOW) or external (HIGH) data clock.
14 D5/INVSYNC bidirectional Parallel data bit 5 when SER/PAR is LOW; when SER/PAR is HIGH it selects the active state of SYNC.
15 D6/INVSCLK bidirectional Parallel data bit 6 when SER/PAR is LOW; when SER/PAR is HIGH it inverts the SCLK signal in master and slave modes.
16 D7/RDC/SDIN bidirectional Parallel data bit 7 when SER/PAR is LOW; when SER/PAR is HIGH it is the serial data input or read mode select.
17 OGND power_in Input/output interface digital power ground.
18 OVDD power_in Input/output interface digital power, nominally the same supply as the host interface (5 V or 3 V).
19 DVDD power_in Digital power, nominally 5 V.
20 DGND power_in Digital power ground.
21 D8/SDOUT output Parallel data bit 8 when SER/PAR is LOW; serial data output synchronized to SCLK when SER/PAR is HIGH.
22 D9/SCLK bidirectional Parallel data bit 9 when SER/PAR is LOW; serial data clock input or output when SER/PAR is HIGH, depending on EXT/INT.
23 D10/SYNC output Parallel data bit 10 when SER/PAR is LOW; digital frame synchronization output for the internal data clock in serial mode.
24 D11/RDERROR output Parallel data bit 11 when SER/PAR is LOW; incomplete read error flag in serial slave mode when EXT/INT is HIGH.
25 D12 output Bit 12 of the parallel port data output bus, high impedance when SER/PAR is HIGH.
26 D13 output Bit 13 of the parallel port data output bus, high impedance when SER/PAR is HIGH.
27 D14 output Bit 14 of the parallel port data output bus, high impedance when SER/PAR is HIGH.
28 D15 output Bit 15 of the parallel port data output bus, high impedance when SER/PAR is HIGH.
29 BUSY output Busy output that goes HIGH at conversion start and stays HIGH until the data is latched; its falling edge can be used as a data-ready clock.
30 DGND power_in Must be tied to digital ground.
31 RD input Read data input; when CS and RD are both LOW the interface output bus is enabled.
32 CS input Chip select input; when CS and RD are both LOW the output bus is enabled, and CS also gates the external clock.
33 RESET input Reset input; when HIGH it resets the AD7663 and aborts any current conversion, and may be tied to DGND if unused.
34 PD input Power-down input; when HIGH power consumption is reduced and conversions are inhibited after the current one completes.
35 CNVST input Start conversion input; the next falling edge after acquisition starts the conversion, with the behavior depending on the CNVST level at the end of acquisition.
36 AGND power_in Must be tied to analog ground.
37 REF passive Reference input voltage.
38 REFGND power_in Reference input analog ground; should be a low impedance return because it carries pulsed currents.
39 INGND power_in Analog input ground used to sense the analog input signal.
40 INA passive Analog input; refer to Table I for the input range configuration.
41 INB passive Analog input; refer to Table I for the input range configuration.
42 INC passive Analog input; refer to Table I for the input range configuration.
43 IND passive Analog input; refer to Table I for the input range configuration.
44 NC unconnected No connect.
45 NC unconnected No connect.
46 NC unconnected No connect.
47 NC unconnected No connect.
48 NC unconnected No connect.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LQFP-48(7x7)
Category Data Converters
Pins 48

CAD (KiCad official)

  • Symbol: AD7663ASTZ
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ad7663astz-etched.step / ad7663astz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7663astz.step / ad7663astz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (24 pp, sha256 7c94e5d758caa492, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF