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AD7656YSTZ-1

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Analog Devices Analog To Digital Converters (ADCs), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata convertersad7656ystz-1factory-2.0.0extractor-text

Verified AD7656YSTZ-1

by Ray · last 2 Nov 2026 · 1 record · files match
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Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 64 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD7656YSTZ-1 · LQFP-64(10x10) · 64 pins
  • ✓copper: 64 copper pads, none touching another net
  • ✓datasheet: all 64 pin names found in the 32-page datasheet
  • ✓distributor: lcsc C651337, digikey 505-AD7656YSTZ-1-ND, mouser 584-AD7656YSTZ-1
  • ✓family: LQFP-64_10x10mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-h6enrya1/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 64 pins = 64 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 64 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad7656ystz-1.kicad_sym✓ ad7656ystz-1.kicad_mod✓ ad7656ystz-1.step
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AD7656YSTZ-1

Analog Devices · Analog To Digital Converters (ADCs) · LQFP-64(10x10)

AD7656YSTZ-1 from Analog Devices, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DB14/REFBUFEN/DIS bidirectional Data bit 14 in parallel mode is a three-state digital I/O, and in serial mode it enables or disables the internal reference buffers.
2 DB13 bidirectional Data bit 13 is a three-state parallel I/O that must be tied to DGND when the serial interface is selected.
3 DB12 bidirectional Data bit 12 is a three-state parallel I/O that must be tied to DGND when the serial interface is selected.
4 DB11 bidirectional Data bit 11 is a three-state parallel I/O, and in serial mode it must be tied to DGND.
5 DB10/DOUT C bidirectional Data bit 10 is a three-state parallel I/O, and in serial mode it outputs serial conversion data DOUT C when SEL C = 1.
6 DB9/DOUT B bidirectional Data bit 9 is a three-state parallel I/O, and in serial mode it outputs serial conversion data DOUT B when SEL B = 1.
7 DB8/DOUT A bidirectional Data bit 8 is a three-state parallel I/O, and in serial mode it outputs serial conversion data DOUT A when SEL A = 1.
8 DGND power_in Digital ground is the reference point for all digital circuitry and must be within 0.3 V of AGND, even on a transient basis.
9 VDRIVE power_in Logic power supply input sets the interface operating voltage, specified at 2.7 V to 5.25 V, and must not exceed DVCC + 0.3 V.
10 DB7/HBEN/DCEN bidirectional Data bit 7 in word mode, HBEN in byte mode, or DCEN in serial mode, where logic high enables daisy-chain operation.
11 DB6/SCLK bidirectional Data bit 6 in parallel mode, and in serial mode it is the read serial clock SCLK input.
12 DB5/DCIN A bidirectional Data bit 5 in parallel mode, and in serial daisy-chain mode it is the Daisy-Chain Input A; tie to DGND if daisy-chain is unused.
13 DB4/DCIN B bidirectional Data bit 4 in parallel mode, and in serial daisy-chain mode it is the Daisy-Chain Input B; tie to DGND if daisy-chain is unused.
14 DB3/DCIN C bidirectional Data bit 3 in parallel mode, and in serial daisy-chain mode it is the Daisy-Chain Input C; tie to DGND if daisy-chain is unused.
15 DB2/SEL C bidirectional Data bit 2 in parallel mode, and in serial mode it selects whether DOUT C is enabled as a serial output.
16 DB1/SEL B bidirectional Data bit 1 in parallel mode, and in serial mode it selects whether DOUT B is enabled as a serial output; must be 1 for the serial interface.
17 DB0/SEL A bidirectional Data bit 0 in parallel mode, and in serial mode it must be set to 1 to enable DOUT A as a serial output.
18 BUSY output Busy output goes high when a conversion starts and stays high until the data is latched, and CONVST edges are ignored while it is high.
19 CS input Active-low chip select frames the data transfer, enabling the parallel output bus with RD or writing the control register with WR.
20 RD input Active-low read data enables the parallel output bus when CS is also low; it must be held low in serial mode.
21 CONVST C input Conversion start input C initiates simultaneous conversions on V5 and V6 on a low-to-high edge.
22 CONVST B input Conversion start input B initiates simultaneous conversions on V3 and V4 on a low-to-high edge.
23 CONVST A input Conversion start input A initiates simultaneous conversions on V1 and V2 on a low-to-high edge.
24 STBY input Standby mode input puts all six ADCs into standby when low and is high for normal operation.
25 DGND power_in Digital ground is the reference point for all digital circuitry and must be within 0.3 V of AGND, even on a transient basis.
26 DVCC power_in Digital power supply is specified at 4.75 V to 5.25 V and must be within 0.3 V of AVCC, even on a transient basis.
27 RANGE input Analog input range select sets ±2 × VREF when high and ±4 × VREF when low, sampled on the falling edge of BUSY in hardware mode.
28 RESET input Reset input resets the device when high, requiring a roughly 100 ns pulse after power-up before the first conversion.
29 W/B input Word/byte input selects 16-bit word transfers when low and byte transfers when high in parallel mode; tie to DGND in serial mode.
30 VSS power_in Negative analog input supply, specified as −10 V to −16.5 V for the ±4 × VREF range and −5 V to −16.5 V for the ±2 × VREF range.
31 VDD power_in Positive analog input supply, specified as 10 V to 16.5 V for the ±4 × VREF range and 5 V to 16.5 V for the ±2 × VREF range.
32 AGND power_in Analog ground is the reference point for all analog circuitry and must be within 0.3 V of DGND.
33 V1 input Analog input 1 is a single-ended bipolar input whose range is set by the RANGE pin or RNGC to RNGA control bits.
34 AVCC power_in Analog supply for the ADC cores is specified at 4.75 V to 5.25 V and must be within 0.3 V of DVCC.
35 AVCC power_in Analog supply for the ADC cores is specified at 4.75 V to 5.25 V and must be within 0.3 V of DVCC.
36 V2 input Analog input 2 is a single-ended bipolar input whose range is set by the RANGE pin or RNGC to RNGA control bits.
37 AGND power_in Analog ground is the reference point for all analog circuitry and must be within 0.3 V of DGND.
38 AGND power_in Analog ground is the reference point for all analog circuitry and must be within 0.3 V of DGND.
39 V3 input Analog input 3 is a single-ended bipolar input whose range is set by the RANGE pin or RNGC to RNGA control bits.
40 AVCC power_in Analog supply for the ADC cores is specified at 4.75 V to 5.25 V and must be within 0.3 V of DVCC.
41 AVCC power_in Analog supply for the ADC cores is specified at 4.75 V to 5.25 V and must be within 0.3 V of DVCC.
42 V4 input Analog input 4 is a single-ended bipolar input whose range is set by the RANGE pin or RNGC to RNGA control bits.
43 AGND power_in Analog ground is the reference point for all analog circuitry and must be within 0.3 V of DGND.
44 AGND power_in Analog ground is the reference point for all analog circuitry and must be within 0.3 V of DGND.
45 V5 input Analog input 5 is a single-ended bipolar input whose range is set by the RANGE pin or RNGC to RNGA control bits.
46 AVCC power_in Analog supply for the ADC cores is specified at 4.75 V to 5.25 V and must be within 0.3 V of DVCC.
47 AVCC power_in Analog supply for the ADC cores is specified at 4.75 V to 5.25 V and must be within 0.3 V of DVCC.
48 V6 input Analog input 6 is a single-ended bipolar input whose range is set by the RANGE pin or RNGC to RNGA control bits.
49 AGND power_in Analog ground is the reference point for all analog circuitry and must be within 0.3 V of DGND.
50 AVCC power_in Analog supply for the ADC cores is specified at 4.75 V to 5.25 V and must be within 0.3 V of DVCC.
51 REFIN/REFOUT bidirectional Reference input/output carries the on-chip 2.5 V reference, which can be disabled to accept an external reference and must be decoupled with at least 1 µF when enabled.
52 AGND power_in Analog ground is the reference point for all analog circuitry and must be within 0.3 V of DGND.
53 AGND power_in Analog ground is the reference point for all analog circuitry and must be within 0.3 V of DGND.
54 REFCAPA passive Reference capacitor A decouples the reference buffer for ADC pair A and must be decoupled to AGND with a 1 µF capacitor.
55 AGND power_in Analog ground is the reference point for all analog circuitry and must be within 0.3 V of DGND.
56 REFCAPB passive Reference capacitor B decouples the reference buffer for ADC pair B and must be decoupled to AGND with a 1 µF capacitor.
57 AGND power_in Analog ground is the reference point for all analog circuitry and must be within 0.3 V of DGND.
58 REFCAPC passive Reference capacitor C decouples the reference buffer for ADC pair C and must be decoupled to AGND with a 1 µF capacitor.
59 AGND power_in Analog ground is the reference point for all analog circuitry and must be within 0.3 V of DGND.
60 AVCC power_in Analog supply for the ADC cores is specified at 4.75 V to 5.25 V and must be within 0.3 V of DVCC.
61 SER/PAR SEL input Serial/parallel select input chooses the parallel interface when low and the serial interface when high.
62 H/S SEL input Hardware/software select input uses CONVST pins to select ADC pairs when low and the control register when high.
63 WR/REFEN/DIS input Write data/reference enable input writes DB[15:8] to the control register with CS and WR low in software mode, and enables or disables the internal reference in hardware mode.
64 DB15 bidirectional Data bit 15 is a three-state parallel I/O that must be tied to DGND when the serial interface is selected, and carries a leading 0 on the AD7657-1 and AD7658-1 only in its variant-specific data format.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LQFP-64(10x10)
Category Data Converters
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Positive Full-Scale Error -0.8 0.381 0.8 % FSR 3
Positive Full-Scale Error Matching -0.35 0.35 % FSR 3
Bipolar Zero-Scale Error -0.048 0.0137 0.048 % FSR Y Version 3
Bipolar Zero-Scale Error Matching -0.038 0.038 % FSR 3
Negative Full-Scale Error -0.8 0.381 0.8 % FSR 3
Negative Full-Scale Error Matching -0.35 0.35 % FSR 3
Integral Nonlinearity -3 3 LSB 3
Integral Nonlinearity -1 1 LSB 3
DC Leakage Current -1 1 µA 3
Reference Output Voltage 2.49 2.51 V 3
Reference Temperature Coefficient 6 25 ppm/°C 3
Input Current IIN -10 10 µA Typically 10 nA, VIN = 0 V or VDRIVE 4
Output Low Voltage VOL 0.2 V ISINK = 200 µA 4
Floating-State Leakage Current -10 10 µA 4
VDD VDD -5 16.5 V For the 4 × VREF range, VDD = 10 V to 16.5 V 4
VSS VSS -16.5 -5 V For the 4 × VREF range, VSS = -10 V to -16.5 V 4
AVCC AVCC 4.75 5.25 V 4
DVCC DVCC 4.75 5.25 V 4
VDRIVE VDRIVE 2.7 5.25 V 4
Operating Temperature Range TA -40 125 °C Y Version 10
VDD to AGND, DGND -0.3 16.5 V 10
VSS to AGND, DGND -16.5 0.3 V 10
AVCC to AGND, DGND -0.3 7 V 10
DVCC to DGND, AGND -0.3 7 V 10
AGND to DGND -0.3 0.3 V 10
Input Current to Any Pin Except Supplies -10 10 mA Transient currents of up to 100 mA do not cause SCR latch-up 10
Storage Temperature Range -65 150 °C 10
Junction Temperature 150 °C 10
Pb/Sn Temperature, Soldering Reflow 240 °C 10 sec to 30 sec 10
Pb-Free Temperature, Soldering Reflow 260 °C 10
Thermal Resistance Junction-to-Ambient θJA 45 °C/W 64-lead LQFP, 4-layer board 10
Thermal Resistance Junction-to-Case θJC 11 °C/W 64-lead LQFP 10
Frequency of Serial Read Clock fSCLK 18 MHz 9
Minimum Quiet Time tQUIET 150 ns Between bus relinquish and start of next conversion 9
Acquisition Time tACQ 550 ns 9
Minimum CONVST Low Pulse t10 25 ns 9
CONVST High to BUSY High t1 60 ns 9
Data Hold Time After RD Rising Edge t7 10 ns 9
WR Pulse Width t11 15 ns 9
Data Access Time After SCLK Rising Edge/CS Falling Edge t17 22 ns 9

CAD (KiCad official)

  • Symbol: AD7656YSTZ-1
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ad7656ystz-1-etched.step / ad7656ystz-1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7656ystz-1.step / ad7656ystz-1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (32 pp, sha256 6ed754dce830790a, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF