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AD7656BSTZ-REEL

Analog Devices · Analog To Digital Converters (ADC) · LQFP-64(10x10)

AD7656BSTZ-REEL from Analog Devices, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DB14/REFBUFEN/DIS	bidirectional	Parallel data bit 14 is a tri-state digital I/O, and in serial mode (SER/PAR=1) it enables or disables the internal reference buffer; it is a leading zero for the AD7657/AD7658.
2	DB13	bidirectional	Parallel data bit 13 is a tri-state I/O that outputs conversion results when CS and RD are low and is a leading zero for the AD7658; it must be tied to DGND in serial mode.
3	DB12	bidirectional	Parallel data bit 12 is a tri-state I/O that outputs conversion results when CS and RD are low and is a leading zero for the AD7658; it must be tied to DGND in serial mode.
4	DB11	bidirectional	Parallel data bit 11 is a tri-state digital output in parallel mode and must be tied to DGND in serial mode (SER/PAR=1).
5	DB10/DOUT C	bidirectional	In parallel mode this is a tri-state data bit 10; in serial mode with SEL C=1 it outputs serial conversion data on DOUT C.
6	DB9/DOUT B	bidirectional	In parallel mode this is a tri-state data bit 9; in serial mode with SEL B=1 it outputs serial conversion data on DOUT B.
7	DB8/DOUT A	bidirectional	In parallel mode this is a tri-state data bit 8; in serial mode with SEL A=1 it outputs serial conversion data on DOUT A.
8	DGND	power_in	Digital ground reference for all digital circuits; both DGND pins (8 and 25) must connect to the system DGND plane and stay within 0.3 V of AGND.
9	VDRIVE	power_in	Logic interface supply that sets the digital I/O voltage, specified at 2.7 V to 5.25 V, and must be decoupled to DGND with 10 µF and 100 nF capacitors.
10	DB7/HBEN/DCEN	bidirectional	In parallel word mode this is data bit 7; in byte mode it is HBEN selecting the byte order, and in serial mode DCEN=1 enables daisy-chain operation, otherwise it must be tied to DGND.
11	DB6/SCLK	bidirectional	In parallel mode this is tri-state data bit 6; in serial mode (SER/PAR=1) it is the SCLK input that provides the serial read clock.
12	DB5/DCIN A	bidirectional	In parallel mode this is tri-state data bit 5; in serial daisy-chain mode (SER/PAR=1, DCEN=1) it is the DCIN A data input and must otherwise be tied to DGND.
13	DB4/DCIN B	bidirectional	In parallel mode this is tri-state data bit 4; in serial daisy-chain mode (SER/PAR=1, DCEN=1) it is the DCIN B data input and must otherwise be tied to DGND.
14	DB3/DCIN C	bidirectional	In parallel mode this is tri-state data bit 3; in serial daisy-chain mode (SER/PAR=1, DCEN=1) it is the DCIN C data input and must otherwise be tied to DGND.
15	DB2/SEL C	bidirectional	In parallel mode this is tri-state data bit 2; in serial mode it is SEL C, which when set to 1 enables DOUT C as a serial output.
16	DB1/SEL B	bidirectional	In parallel mode this is tri-state data bit 1; in serial mode it is SEL B, which when set to 1 enables DOUT B as a serial output.
17	DB0/SEL A	bidirectional	In parallel mode this is tri-state data bit 0; in serial mode it is SEL A, which must be 1 to enable DOUT A as a serial output.
18	BUSY	output	Goes high when a conversion starts and returns low when conversion ends and data is latched to the output register; no new conversion should be started while BUSY is high.
19	CS	input	Active-low chip select that enables data frame transfers; in parallel mode CS and RD low enable the output bus, and in serial mode it enables each serial frame.
20	RD	input	Active-low read input that enables the parallel output bus together with CS; in serial mode it must be held low.
21	CONVST C	input	Logic input whose rising edge starts simultaneous conversion of the V5 and V6 pair (or the pair selected in software mode), and it can also place that pair in partial power-down.
22	CONVST B	input	Logic input whose rising edge starts simultaneous conversion of the V3 and V4 pair, and it can also place that pair in partial power-down.
23	CONVST A	input	Logic input whose rising edge starts simultaneous conversion of the V1 and V2 pair, and in software mode (H/S SEL=1) it starts conversions of the pairs selected in the control register.
24	STBY	input	Standby input: pulling low puts all six ADCs into standby with maximum 100 µW consumption, and pulling high restores normal operation.
25	DGND	power_in	Digital ground reference for all digital circuits; connect to the system DGND plane together with pin 8 and keep within 0.3 V of AGND.
26	DVCC	power_in	Digital supply of 4.75 V to 5.25 V that must be within 0.3 V of AVCC and decoupled to DGND with 10 µF and 100 nF capacitors.
27	RANGE	input	Input range select sampled at the BUSY falling edge in hardware mode: logic 1 selects ±2 × VREF and logic 0 selects ±4 × VREF.
28	RESET	input	Active-high reset that aborts any conversion and clears internal registers to zero; the device must receive a high RESET pulse after power-up (typically 100 ns wide) followed by a CONVST pulse.
29	W/B	input	Word/byte select: logic low uses 16-bit parallel word mode on DB[15:0], logic high uses byte mode on DB[15:8]; must be tied to DGND in serial mode.
30	VSS	power_in	Negative supply for the analog input section, from −5 V to −16.5 V, which must be at least as large as the selected input range requirement and be decoupled with 10 µF and 100 nF.
31	VDD	power_in	Positive supply for the analog input section, from 5 V to 16.5 V, which must be at least as large as the selected input range requirement and be decoupled with 10 µF and 100 nF.
32	AGND	power_in	Analog ground reference for the analog circuitry and ADC core; all analog inputs and external reference signals are referenced to AGND.
33	V1	input	Single-ended analog input channel 1, with input range ±4 × VREF or ±2 × VREF set by the RANGE pin or the RNGA control bit.
34	AVCC	power_in	Analog supply for the ADC core of 4.75 V to 5.25 V, which should be decoupled to AGND with 10 µF tantalum and 100 nF ceramic capacitors.
35	AVCC	power_in	Analog supply for the ADC core of 4.75 V to 5.25 V, which should be decoupled to AGND with 10 µF tantalum and 100 nF ceramic capacitors.
36	V2	input	Single-ended analog input channel 2, with input range ±4 × VREF or ±2 × VREF set by the RANGE pin or the RNGA control bit.
37	AGND	power_in	Analog ground reference for the analog circuitry and ADC core; all analog inputs and external reference signals are referenced to AGND.
38	AGND	power_in	Analog ground reference for the analog circuitry and ADC core; all analog inputs and external reference signals are referenced to AGND.
39	V3	input	Single-ended analog input channel 3, with input range ±4 × VREF or ±2 × VREF set by the RANGE pin or the RNGB control bit.
40	AVCC	power_in	Analog supply for the ADC core of 4.75 V to 5.25 V, which should be decoupled to AGND with 10 µF tantalum and 100 nF ceramic capacitors.
41	AVCC	power_in	Analog supply for the ADC core of 4.75 V to 5.25 V, which should be decoupled to AGND with 10 µF tantalum and 100 nF ceramic capacitors.
42	V4	input	Single-ended analog input channel 4, with input range ±4 × VREF or ±2 × VREF set by the RANGE pin or the RNGB control bit.
43	AGND	power_in	Analog ground reference for the analog circuitry and ADC core; all analog inputs and external reference signals are referenced to AGND.
44	AGND	power_in	Analog ground reference for the analog circuitry and ADC core; all analog inputs and external reference signals are referenced to AGND.
45	V5	input	Single-ended analog input channel 5, with input range ±4 × VREF or ±2 × VREF set by the RANGE pin or the RNGC control bit.
46	AVCC	power_in	Analog supply for the ADC core of 4.75 V to 5.25 V, which should be decoupled to AGND with 10 µF tantalum and 100 nF ceramic capacitors.
47	AVCC	power_in	Analog supply for the ADC core of 4.75 V to 5.25 V, which should be decoupled to AGND with 10 µF tantalum and 100 nF ceramic capacitors.
48	V6	input	Single-ended analog input channel 6, with input range ±4 × VREF or ±2 × VREF set by the RANGE pin or the RNGC control bit.
49	AGND	power_in	Analog ground reference for the analog circuitry and ADC core; all analog inputs and external reference signals are referenced to AGND.
50	AVCC	power_in	Analog supply for the ADC core of 4.75 V to 5.25 V, which should be decoupled to AGND with 10 µF tantalum and 100 nF ceramic capacitors.
51	REFIN/REFOUT	bidirectional	Reference input/output that provides the on-chip 2.5 V reference when internal reference is enabled, or accepts an external 2.5 V to 3 V reference when it is disabled; decouple with 10 µF and 100 nF when internal reference is used.
52	AGND	power_in	Analog ground reference for the analog circuitry and ADC core; all analog inputs and external reference signals are referenced to AGND.
53	AGND	power_in	Analog ground reference for the analog circuitry and ADC core; all analog inputs and external reference signals are referenced to AGND.
54	REFCAPA	passive	Decoupling connection for the reference buffer of ADC pair A (V1 and V2), which must be decoupled to AGND with 10 µF and 100 nF capacitors.
55	AGND	power_in	Analog ground reference for the analog circuitry and ADC core; all analog inputs and external reference signals are referenced to AGND.
56	REFCAPB	passive	Decoupling connection for the reference buffer of ADC pair B (V3 and V4), which must be decoupled to AGND with 10 µF and 100 nF capacitors.
57	AGND	power_in	Analog ground reference for the analog circuitry and ADC core; all analog inputs and external reference signals are referenced to AGND.
58	REFCAPC	passive	Decoupling connection for the reference buffer of ADC pair C (V5 and V6), which must be decoupled to AGND with 10 µF and 100 nF capacitors.
59	AGND	power_in	Analog ground reference for the analog circuitry and ADC core; all analog inputs and external reference signals are referenced to AGND.
60	AVCC	power_in	Analog supply for the ADC core of 4.75 V to 5.25 V, which should be decoupled to AGND with 10 µF tantalum and 100 nF ceramic capacitors.
61	SER/PAR/SEL	input	Serial/parallel select: logic low selects the parallel interface and logic high selects the serial interface mode.
62	H/S SEL	input	Hardware/software select: logic low selects hardware mode where CONVST pins choose ADC pairs, and logic high selects software mode where the control register chooses pairs and ranges.
63	WR/REFEN/DIS	input	In parallel mode with H/S SEL=1 and CS low this is the write strobe for the control register; with H/S SEL=0 it enables (1) or disables (0) the internal reference.
64	DB15	bidirectional	Parallel data bit 15 (MSB) is a tri-state I/O that outputs conversion results when CS and RD are low; it is a leading zero for the AD7657/AD7658 and must be tied to DGND in serial mode.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LQFP-64(10x10)
Category	Data Acquisition
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Signal-to-noise and distortion (SINAD), B version	SINAD	84	85.5		dB	fIN = 50 kHz sine wave	3
Signal-to-noise ratio (SNR), B version	SNR	85	86.5		dB	fIN = 50 kHz sine wave	3
Total harmonic distortion (THD)	THD		-92	-90	dB	fIN = 50 kHz sine wave; typ at VDD/VSS = ±5 V to ±10 V	3
Aperture delay				10	ns		3
Aperture delay matching				4	ns		3
No missing codes, B version		15			bits	TA = TMIN to TMAX	3
No missing codes at 25°C		16			bits	TA = 25°C	3
Integral nonlinearity (INL)		-3	1	3	LSB		3
Positive full-scale error		-0.75	0.22	0.75	% FSR		3
Positive full-scale error matching		-0.35		0.35	% FSR		3
Bipolar zero-code error		-0.023	0.004	0.023	% FSR		3
Bipolar zero-code error matching		-0.038		0.038	% FSR		3
Negative full-scale error		-0.75	0.22	0.75	% FSR		3
Negative full-scale error matching		-0.35		0.35	% FSR		3
Analog input DC leakage current		-1		1	μA		3
Reference input voltage range		2.5		3	V		3
Reference DC leakage current		-1		1	μA		3
Reference output voltage		2.49		2.51	V		3
Reference temperature coefficient			6	25	ppm/°C		3
Input high voltage (VINH), multiplier of VDRIVE	VINH	0.7			x VDRIVE	Printed as 0.7 × VDRIVE V (minimum)	4
Input low voltage (VINL), multiplier of VDRIVE	VINL			0.3	x VDRIVE	Printed as 0.3 × VDRIVE V (maximum)	4
Input current (IIN)	IIN	-1		1	μA	Typical 10 nA, VIN = 0 V or VDRIVE	4
Input capacitance (CIN), logic inputs	CIN			10	pF		4
Output low voltage (VOL)	VOL			0.2	V	ISINK = 200 µA	4
Conversion time	tCONVERT		3	3.1	μs		4
Acquisition time	tACQ			550	ns	Printed as 最大值 in Table 1; Table 4 lists it as minimum	4
Positive power supply VDD (nominal min/max)	VDD	5		15	V	For ±4 × VREF range, VDD = 10 V to 16.5 V	4
Negative power supply VSS (nominal min/max)	VSS	-15		-5	V	For ±4 × VREF range, VDD = −10 V to −16.5 V	4
Logic interface supply VDRIVE (nominal min/max)	VDRIVE	3		5	V		4
Total supply current, normal mode (static)	ITOTAL			28	mA	Digital inputs 0 V or VDRIVE; AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V	4
Total supply current, normal mode (operating)	ITOTAL			26	mA	fSAMPLE = 250 kSPS; AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V	4
Partial power-down mode supply current				7	mA	AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V	4
Full power-down mode current (STBY pin)				80	μA	SCLK on or off; AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V	4
Power dissipation, normal mode (static)				143	mW	AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V	4
Power dissipation, normal mode (operating)				140	mW	fSAMPLE = 250 kSPS	4
Quiet time, bus release to next conversion start	tQUIET	150			ns	Parallel mode	9
Minimum CONVST low pulse	t10	25			ns		9
Wake-up time, STBY rising edge to CONVST rising edge	tWAKE-UP			2	ms	Partial power-down figure is 25 μs maximum	9
Serial read clock frequency	fSCLK			18	MHz		9
Operating ambient temperature, B version	TA	-40		85	°C	B version (Y version is −40°C to +125°C, not this MPN)	10
AVCC analog supply	AVCC	4.75	5	5.25	V		3
DVCC digital supply	DVCC	4.75	5	5.25	V		3
VDRIVE interface supply	VDRIVE	2.7		5.25	V		3
Positive analog supply VDD, ±2 × VREF range	VDD	5		16.5	V	±2 × VREF range; for ±4 × VREF range VDD = 10 V to 16.5 V	3
Negative analog supply VSS, ±2 × VREF range	VSS	-16.5		-5	V	±2 × VREF range; for ±4 × VREF range VSS = −10 V to −16.5 V	3
VDD to AGND, DGND	VDD	-0.3		16.5	V		10
VSS to AGND, DGND	VSS	-16.5		0.3	V		10
AVCC to AGND, DGND	AVCC	-0.3		7	V		10
DVCC to DGND, AGND	DVCC	-0.3		7	V		10
AGND to DGND		-0.3		0.3	V		10
Input current to any pin except supplies		-10		10	mA	Transients below 100 mA do not cause SCR latch-up	10
Storage temperature range	TSTG	-65		150	°C		10
Junction temperature	TJ			150	°C		10
Thermal resistance, junction-to-ambient, 64-lead LQFP	θJA		45		°C/W	Worst case, device soldered to a 4-layer board	10
Thermal resistance, junction-to-case, 64-lead LQFP	θJC		11		°C/W		10

CAD (KiCad official)

Symbol: AD7656BSTZ-REEL
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: ad7656bstz-reel-etched.step / ad7656bstz-reel-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7656bstz-reel.step / ad7656bstz-reel.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (32 pp, sha256 0b9743f8d413d976, retrieved 2026-10-19, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF