AD7656BSTZ-1

Analog Devices · Analog To Digital Converters (ADC) · LQFP-64(10x10)

AD7656BSTZ-1 from Analog Devices, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DB14/REFBUFEN/DIS	bidirectional	Parallel data bit 14 or reference buffer enable/disable function; detailed text not in the supplied pages.
2	DB13	bidirectional	Parallel data output bit 13; tied to DGND in serial interface mode.
3	DB12	bidirectional	Parallel data output bit 12; tied to DGND in serial interface mode.
4	DB11	bidirectional	Parallel data output bit 11; tied to DGND in serial interface mode.
5	DB10/DOUT C	bidirectional	Parallel data bit 10 when SER/PAR SEL = 0, or serial data output DOUT C when SER/PAR SEL = 1.
6	DB9/DOUT B	bidirectional	Parallel data bit 9 when SER/PAR SEL = 0, or serial data output DOUT B when SER/PAR SEL = 1.
7	DB8/DOUT A	bidirectional	Parallel data bit 8 when SER/PAR SEL = 0, or serial data output DOUT A when SER/PAR SEL = 1.
8	DGND	power_in	Digital ground for digital circuitry; connect to the system DGND plane, within 0.3 V of AGND.
9	VDRIVE	power_in	Logic power supply for the interface, 4.75 V to 5.25 V range per supply description; sets the interface logic output voltage (abs max DGND-0.3 V to DVCC+0.3 V).
10	DB7/HBEN/DCEN	bidirectional	Parallel data bit 7, or HBEN in byte mode (W/B = 1), or DCEN daisy-chain enable in serial mode.
11	DB6/SCLK	bidirectional	Parallel data bit 6 when SER/PAR SEL = 0, or serial clock input when SER/PAR SEL = 1.
12	DB5/DCIN A	bidirectional	Parallel data bit 5, or daisy-chain input A in serial mode when DCEN = 1.
13	DB4/DCIN B	bidirectional	Parallel data bit 4, or daisy-chain input B in serial mode when DCEN = 1.
14	DB3/DCIN C	bidirectional	Parallel data bit 3, or daisy-chain input C in serial mode when DCEN = 1.
15	DB2/SEL C	bidirectional	Parallel data bit 2, or SEL C in serial mode selecting use of DOUT C as a serial output.
16	DB1/SEL B	bidirectional	Parallel data bit 1, or SEL B in serial mode selecting use of DOUT B as a serial output.
17	DB0/SEL A	bidirectional	Parallel data bit 0, or SEL A in serial mode selecting use of DOUT A as a serial output.
18	BUSY	output	Busy output that goes high when conversion starts and returns low when conversion data is latched into the output register.
19	CS	input	Chip select input, active low; with RD it enables reading the conversion result and with WR it enables writes.
20	RD	input	Read input, active low; used with CS to read conversion results.
21	CONVST C	input	Conversion start input C that starts simultaneous conversion of V5 and V6.
22	CONVST B	input	Conversion start input B that starts simultaneous conversion of V3 and V4.
23	CONVST A	input	Conversion start input A that starts simultaneous conversion of V1 and V2.
24	STBY	input	Standby mode input; function text not in the supplied pages.
25	DGND	power_in	Digital ground for digital circuitry; connect to the system DGND plane, within 0.3 V of AGND.
26	DVCC	power_in	Digital supply voltage 4.75 V to 5.25 V; decouple to DGND with a 1 uF capacitor and keep within 0.3 V of AVCC.
27	RANGE	input	Analog input range select in hardware mode, setting the range of V1 to V6 (+/-4xVREF or +/-2xVREF); detail text not in supplied pages.
28	RESET	input	Reset input; function text not in the supplied pages.
29	W/B	input	Word/byte select for the parallel interface (W/B = 0 word mode, W/B = 1 byte mode with HBEN).
30	VSS	power_in	Negative power supply for the high voltage analog input structure; abs max +0.3 V to -16.5 V relative to AGND/DGND.
31	VDD	power_in	Positive power supply for the high voltage analog input structure; abs max -0.3 V to +16.5 V relative to AGND/DGND.
32	AGND	power_in	Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND.
33	V1	input	Analog input 1, single-ended; range set by RANGE pin (hardware mode) or control register (software mode).
34	AVCC	power_in	Analog supply voltage 4.75 V to 5.25 V; decouple to AGND and keep within 0.3 V of DVCC.
35	AVCC	power_in	Analog supply voltage 4.75 V to 5.25 V; decouple to AGND and keep within 0.3 V of DVCC.
36	V2	input	Analog input 2, single-ended; range set by RANGE pin (hardware mode) or control register (software mode).
37	AGND	power_in	Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND.
38	AGND	power_in	Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND.
39	V3	input	Analog input 3, single-ended; range set by RANGE pin (hardware mode) or control register (software mode).
40	AVCC	power_in	Analog supply voltage 4.75 V to 5.25 V; decouple to AGND and keep within 0.3 V of DVCC.
41	AVCC	power_in	Analog supply voltage 4.75 V to 5.25 V; decouple to AGND and keep within 0.3 V of DVCC.
42	V4	input	Analog input 4, single-ended; range set by RANGE pin (hardware mode) or control register (software mode).
43	AGND	power_in	Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND.
44	AGND	power_in	Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND.
45	V5	input	Analog input 5, single-ended; range set by RANGE pin (hardware mode) or control register (software mode).
46	AVCC	power_in	Analog supply voltage 4.75 V to 5.25 V; decouple to AGND and keep within 0.3 V of DVCC.
47	AVCC	power_in	Analog supply voltage 4.75 V to 5.25 V; decouple to AGND and keep within 0.3 V of DVCC.
48	V6	input	Analog input 6, single-ended; range set by RANGE pin (hardware mode) or control register (software mode).
49	AGND	power_in	Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND.
50	AVCC	power_in	Analog supply voltage 4.75 V to 5.25 V; decouple to AGND and keep within 0.3 V of DVCC.
51	REFIN/REFOUT	bidirectional	Reference input or 2.5 V internal reference output; decouple to AGND with a 1 uF capacitor (abs max -0.3 V to AVCC+0.3 V).
52	AGND	power_in	Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND.
53	AGND	power_in	Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND.
54	REFCAPA	passive	Reference decoupling capacitor A pin; connect a 1 uF capacitor to AGND, used for the ADC pair converted by CONVST A.
55	AGND	power_in	Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND.
56	REFCAPB	passive	Reference decoupling capacitor B pin; connect a 1 uF capacitor to AGND.
57	AGND	power_in	Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND.
58	REFCAPC	passive	Reference decoupling capacitor C pin; connect a 1 uF capacitor to AGND.
59	AGND	power_in	Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND.
60	AVCC	power_in	Analog supply voltage 4.75 V to 5.25 V; decouple to AGND and keep within 0.3 V of DVCC.
61	SER/PAR SEL	input	Interface select: logic low selects parallel interface, logic high selects serial interface.
62	H/S SEL	input	Hardware/software select: logic high uses DB[15:8] with CS and WR to write the control register; logic low selects hardware mode.
63	WR/REFEN/DIS	input	Write input in software mode, or internal reference enable/disable when H/S SEL = 0 (REFEN/DIS = 0 uses external reference, 1 enables internal reference).
64	DB15	bidirectional	Parallel data output bit 15 (MSB); tied to DGND in serial interface mode.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LQFP-64(10x10)
Category	Data Acquisition
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Signal-to-noise and distortion (SINAD)	SINAD	88			dB	fIN = 10 kHz	3
Signal-to-noise ratio (SNR)	SNR	88			dB	fIN = 10 kHz	3
Total harmonic distortion (THD)	THD			-90	dB	fIN = 10 kHz	3
Total harmonic distortion (THD)	THD			-105	dB	VDD/VSS = ±5 V to ±16.5 V	3
Spurious-free dynamic range (SFDR)	SFDR			-100	dB	fIN = 10 kHz	3
Intermodulation distortion, second-order terms	IMD			-112	dB	fa = 10.5 kHz, fb = 9.5 kHz	3
Intermodulation distortion, third-order terms	IMD			-107	dB	fa = 10.5 kHz, fb = 9.5 kHz	3
Channel-to-channel isolation (crosstalk)				-100	dB	Adjacent channel, fIN up to 100 kHz	3
No missing codes		15			bits	B grade	3
Integral nonlinearity (INL)	INL	-3		3	LSB		3
Differential nonlinearity (DNL)	DNL	-1		1	LSB		3
Positive full-scale error		-0.8		0.8	% FS		3
Positive full-scale error matching		-0.35		0.35	% FS		3
Bipolar zero error		-0.048		0.048	% FS	B grade	3
Bipolar zero error matching		-0.038		0.038	% FS		3
Negative full-scale error		-0.8		0.8	% FS		3
Negative full-scale error matching		-0.35		0.35	% FS		3
Analog input current (leakage)		-1		1	μA		3
Reference output voltage		2.49		2.51	V		3
Input current (digital)	IIN	-10		10	μA	VIN = 0 V to VDRIVE	4
Output low voltage	VOL			0.2	V	ISINK = 200 μA	4
Floating-state output leakage current		-10		10	μA		4
Throughput rate				250	kSPS		4
Total supply current	ITOTAL			18	mA	Digital inputs = 0 V or VDRIVE; AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, VSS = −16.5 V	4
Total supply current at 250 kSPS	ITOTAL			26	mA	fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, VSS = −16.5 V	4
VSS supply current	ISS			0.25	mA	VSS = −16.5 V, fSAMPLE = 250 kSPS	4
VDD supply current	IDD			0.25	mA	VDD = +16.5 V, fSAMPLE = 250 kSPS	4
Standby current				7	mA	AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, VSS = −16.5 V	4
Full shutdown current (STBY low)				60	μA	SCLK inactive, AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, VSS = −16.5 V	4
Power dissipation, normal operation				94	mW	AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, VSS = −16.5 V	4
Power dissipation at 250 kSPS				140	mW	fSAMPLE = 250 kSPS	4
Power dissipation, standby				40	mW		4
Power dissipation, full shutdown (STBY low)				315	μW		4
VDD supply voltage	VDD	-5		16.5	V	±4 × VREF range, VDD = 10 V to 16.5 V	4
VSS supply voltage	VSS	-16.5		-5	V	±4 × VREF range, VSS = −10 V to −16.5 V	4
Analog supply voltage	AVCC	4.75		5.25	V		4
Digital supply voltage	DVCC	4.75		5.25	V		4
Digital interface supply voltage	VDRIVE	2.7		5.25	V		4
Operating temperature range	TA	-40		85	°C	B grade	10
VDD to AGND, DGND	VDD	-0.3		16.5	V		10
VSS to AGND, DGND	VSS	-16.5		0.3	V		10
AVCC to AGND, DGND	AVCC	-0.3		7	V		10
DVCC to DGND, AGND	DVCC	-0.3		7	V		10
AGND to DGND		-0.3		0.3	V		10
Digital input voltage to DGND		-0.3			V	Upper limit VDRIVE + 0.3 V	10
Digital output voltage to DGND		-0.3			V	Upper limit VDRIVE + 0.3 V	10
REFIN/REFOUT to AGND		-0.3			V	Upper limit AVCC + 0.3 V	10
Input current to any pin except supplies		-10		10	mA		10
Storage temperature range		-65		150	°C		10
Junction temperature				150	°C		10
Lead temperature, soldering				240	°C	10 s to 30 s	10
Reflow peak temperature				260	°C		10
ESD rating				1.5	kV		10
Thermal resistance, junction-to-ambient (LQFP-64)	θJA		45		°C/W		10
Thermal resistance, junction-to-case (LQFP-64)	θJC		11		°C/W		10
Conversion time	tCONVERT			3	μs	VDRIVE = 4.75 V to 5.25 V	9
Quiet time before CONVST	tQUIET	150			ns	VDRIVE = 4.75 V to 5.25 V	9
Acquisition time	tACQ	550			ns	VDRIVE = 4.75 V to 5.25 V	9
CONVST pulse spacing	t10	25			ns	VDRIVE = 4.75 V to 5.25 V	9
CONVST rising edge to BUSY rising edge delay	t1			60	ns	VDRIVE = 4.75 V to 5.25 V	9
Wake-up time from STBY	tWAKE-UP			2	ms	VDRIVE = 4.75 V to 5.25 V	9
Serial clock frequency	fSCLK			18	MHz	VDRIVE = 4.75 V to 5.25 V	9

CAD (KiCad official)

Symbol: AD7656BSTZ-1
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: ad7656bstz-1-etched.step / ad7656bstz-1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7656bstz-1.step / ad7656bstz-1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (32 pp, sha256 67071afe34b463ae, retrieved 2026-10-19, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# AD7656BSTZ-1

**Analog Devices** · Analog To Digital Converters (ADC) · LQFP-64(10x10)

AD7656BSTZ-1 from Analog Devices, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DB14/REFBUFEN/DIS | bidirectional | Parallel data bit 14 or reference buffer enable/disable function; detailed text not in the supplied pages. |
| 2 | DB13 | bidirectional | Parallel data output bit 13; tied to DGND in serial interface mode. |
| 3 | DB12 | bidirectional | Parallel data output bit 12; tied to DGND in serial interface mode. |
| 4 | DB11 | bidirectional | Parallel data output bit 11; tied to DGND in serial interface mode. |
| 5 | DB10/DOUT C | bidirectional | Parallel data bit 10 when SER/PAR SEL = 0, or serial data output DOUT C when SER/PAR SEL = 1. |
| 6 | DB9/DOUT B | bidirectional | Parallel data bit 9 when SER/PAR SEL = 0, or serial data output DOUT B when SER/PAR SEL = 1. |
| 7 | DB8/DOUT A | bidirectional | Parallel data bit 8 when SER/PAR SEL = 0, or serial data output DOUT A when SER/PAR SEL = 1. |
| 8 | DGND | power_in | Digital ground for digital circuitry; connect to the system DGND plane, within 0.3 V of AGND. |
| 9 | VDRIVE | power_in | Logic power supply for the interface, 4.75 V to 5.25 V range per supply description; sets the interface logic output voltage (abs max DGND-0.3 V to DVCC+0.3 V). |
| 10 | DB7/HBEN/DCEN | bidirectional | Parallel data bit 7, or HBEN in byte mode (W/B = 1), or DCEN daisy-chain enable in serial mode. |
| 11 | DB6/SCLK | bidirectional | Parallel data bit 6 when SER/PAR SEL = 0, or serial clock input when SER/PAR SEL = 1. |
| 12 | DB5/DCIN A | bidirectional | Parallel data bit 5, or daisy-chain input A in serial mode when DCEN = 1. |
| 13 | DB4/DCIN B | bidirectional | Parallel data bit 4, or daisy-chain input B in serial mode when DCEN = 1. |
| 14 | DB3/DCIN C | bidirectional | Parallel data bit 3, or daisy-chain input C in serial mode when DCEN = 1. |
| 15 | DB2/SEL C | bidirectional | Parallel data bit 2, or SEL C in serial mode selecting use of DOUT C as a serial output. |
| 16 | DB1/SEL B | bidirectional | Parallel data bit 1, or SEL B in serial mode selecting use of DOUT B as a serial output. |
| 17 | DB0/SEL A | bidirectional | Parallel data bit 0, or SEL A in serial mode selecting use of DOUT A as a serial output. |
| 18 | BUSY | output | Busy output that goes high when conversion starts and returns low when conversion data is latched into the output register. |
| 19 | CS | input | Chip select input, active low; with RD it enables reading the conversion result and with WR it enables writes. |
| 20 | RD | input | Read input, active low; used with CS to read conversion results. |
| 21 | CONVST C | input | Conversion start input C that starts simultaneous conversion of V5 and V6. |
| 22 | CONVST B | input | Conversion start input B that starts simultaneous conversion of V3 and V4. |
| 23 | CONVST A | input | Conversion start input A that starts simultaneous conversion of V1 and V2. |
| 24 | STBY | input | Standby mode input; function text not in the supplied pages. |
| 25 | DGND | power_in | Digital ground for digital circuitry; connect to the system DGND plane, within 0.3 V of AGND. |
| 26 | DVCC | power_in | Digital supply voltage 4.75 V to 5.25 V; decouple to DGND with a 1 uF capacitor and keep within 0.3 V of AVCC. |
| 27 | RANGE | input | Analog input range select in hardware mode, setting the range of V1 to V6 (+/-4xVREF or +/-2xVREF); detail text not in supplied pages. |
| 28 | RESET | input | Reset input; function text not in the supplied pages. |
| 29 | W/B | input | Word/byte select for the parallel interface (W/B = 0 word mode, W/B = 1 byte mode with HBEN). |
| 30 | VSS | power_in | Negative power supply for the high voltage analog input structure; abs max +0.3 V to -16.5 V relative to AGND/DGND. |
| 31 | VDD | power_in | Positive power supply for the high voltage analog input structure; abs max -0.3 V to +16.5 V relative to AGND/DGND. |
| 32 | AGND | power_in | Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND. |
| 33 | V1 | input | Analog input 1, single-ended; range set by RANGE pin (hardware mode) or control register (software mode). |
| 34 | AVCC | power_in | Analog supply voltage 4.75 V to 5.25 V; decouple to AGND and keep within 0.3 V of DVCC. |
| 35 | AVCC | power_in | Analog supply voltage 4.75 V to 5.25 V; decouple to AGND and keep within 0.3 V of DVCC. |
| 36 | V2 | input | Analog input 2, single-ended; range set by RANGE pin (hardware mode) or control register (software mode). |
| 37 | AGND | power_in | Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND. |
| 38 | AGND | power_in | Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND. |
| 39 | V3 | input | Analog input 3, single-ended; range set by RANGE pin (hardware mode) or control register (software mode). |
| 40 | AVCC | power_in | Analog supply voltage 4.75 V to 5.25 V; decouple to AGND and keep within 0.3 V of DVCC. |
| 41 | AVCC | power_in | Analog supply voltage 4.75 V to 5.25 V; decouple to AGND and keep within 0.3 V of DVCC. |
| 42 | V4 | input | Analog input 4, single-ended; range set by RANGE pin (hardware mode) or control register (software mode). |
| 43 | AGND | power_in | Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND. |
| 44 | AGND | power_in | Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND. |
| 45 | V5 | input | Analog input 5, single-ended; range set by RANGE pin (hardware mode) or control register (software mode). |
| 46 | AVCC | power_in | Analog supply voltage 4.75 V to 5.25 V; decouple to AGND and keep within 0.3 V of DVCC. |
| 47 | AVCC | power_in | Analog supply voltage 4.75 V to 5.25 V; decouple to AGND and keep within 0.3 V of DVCC. |
| 48 | V6 | input | Analog input 6, single-ended; range set by RANGE pin (hardware mode) or control register (software mode). |
| 49 | AGND | power_in | Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND. |
| 50 | AVCC | power_in | Analog supply voltage 4.75 V to 5.25 V; decouple to AGND and keep within 0.3 V of DVCC. |
| 51 | REFIN/REFOUT | bidirectional | Reference input or 2.5 V internal reference output; decouple to AGND with a 1 uF capacitor (abs max -0.3 V to AVCC+0.3 V). |
| 52 | AGND | power_in | Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND. |
| 53 | AGND | power_in | Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND. |
| 54 | REFCAPA | passive | Reference decoupling capacitor A pin; connect a 1 uF capacitor to AGND, used for the ADC pair converted by CONVST A. |
| 55 | AGND | power_in | Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND. |
| 56 | REFCAPB | passive | Reference decoupling capacitor B pin; connect a 1 uF capacitor to AGND. |
| 57 | AGND | power_in | Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND. |
| 58 | REFCAPC | passive | Reference decoupling capacitor C pin; connect a 1 uF capacitor to AGND. |
| 59 | AGND | power_in | Analog ground reference for on-chip circuitry; connect to the system AGND plane, within 0.3 V of DGND. |
| 60 | AVCC | power_in | Analog supply voltage 4.75 V to 5.25 V; decouple to AGND and keep within 0.3 V of DVCC. |
| 61 | SER/PAR SEL | input | Interface select: logic low selects parallel interface, logic high selects serial interface. |
| 62 | H/S SEL | input | Hardware/software select: logic high uses DB[15:8] with CS and WR to write the control register; logic low selects hardware mode. |
| 63 | WR/REFEN/DIS | input | Write input in software mode, or internal reference enable/disable when H/S SEL = 0 (REFEN/DIS = 0 uses external reference, 1 enables internal reference). |
| 64 | DB15 | bidirectional | Parallel data output bit 15 (MSB); tied to DGND in serial interface mode. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LQFP-64(10x10) |
| Category | Data Acquisition |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Signal-to-noise and distortion (SINAD) | SINAD | 88 |  |  | dB | fIN = 10 kHz | 3 |
| Signal-to-noise ratio (SNR) | SNR | 88 |  |  | dB | fIN = 10 kHz | 3 |
| Total harmonic distortion (THD) | THD |  |  | -90 | dB | fIN = 10 kHz | 3 |
| Total harmonic distortion (THD) | THD |  |  | -105 | dB | VDD/VSS = ±5 V to ±16.5 V | 3 |
| Spurious-free dynamic range (SFDR) | SFDR |  |  | -100 | dB | fIN = 10 kHz | 3 |
| Intermodulation distortion, second-order terms | IMD |  |  | -112 | dB | fa = 10.5 kHz, fb = 9.5 kHz | 3 |
| Intermodulation distortion, third-order terms | IMD |  |  | -107 | dB | fa = 10.5 kHz, fb = 9.5 kHz | 3 |
| Channel-to-channel isolation (crosstalk) |  |  |  | -100 | dB | Adjacent channel, fIN up to 100 kHz | 3 |
| No missing codes |  | 15 |  |  | bits | B grade | 3 |
| Integral nonlinearity (INL) | INL | -3 |  | 3 | LSB |  | 3 |
| Differential nonlinearity (DNL) | DNL | -1 |  | 1 | LSB |  | 3 |
| Positive full-scale error |  | -0.8 |  | 0.8 | % FS |  | 3 |
| Positive full-scale error matching |  | -0.35 |  | 0.35 | % FS |  | 3 |
| Bipolar zero error |  | -0.048 |  | 0.048 | % FS | B grade | 3 |
| Bipolar zero error matching |  | -0.038 |  | 0.038 | % FS |  | 3 |
| Negative full-scale error |  | -0.8 |  | 0.8 | % FS |  | 3 |
| Negative full-scale error matching |  | -0.35 |  | 0.35 | % FS |  | 3 |
| Analog input current (leakage) |  | -1 |  | 1 | μA |  | 3 |
| Reference output voltage |  | 2.49 |  | 2.51 | V |  | 3 |
| Input current (digital) | IIN | -10 |  | 10 | μA | VIN = 0 V to VDRIVE | 4 |
| Output low voltage | VOL |  |  | 0.2 | V | ISINK = 200 μA | 4 |
| Floating-state output leakage current |  | -10 |  | 10 | μA |  | 4 |
| Throughput rate |  |  |  | 250 | kSPS |  | 4 |
| Total supply current | ITOTAL |  |  | 18 | mA | Digital inputs = 0 V or VDRIVE; AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, VSS = −16.5 V | 4 |
| Total supply current at 250 kSPS | ITOTAL |  |  | 26 | mA | fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, VSS = −16.5 V | 4 |
| VSS supply current | ISS |  |  | 0.25 | mA | VSS = −16.5 V, fSAMPLE = 250 kSPS | 4 |
| VDD supply current | IDD |  |  | 0.25 | mA | VDD = +16.5 V, fSAMPLE = 250 kSPS | 4 |
| Standby current |  |  |  | 7 | mA | AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, VSS = −16.5 V | 4 |
| Full shutdown current (STBY low) |  |  |  | 60 | μA | SCLK inactive, AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, VSS = −16.5 V | 4 |
| Power dissipation, normal operation |  |  |  | 94 | mW | AVCC = DVCC = VDRIVE = +5.25 V, VDD = +16.5 V, VSS = −16.5 V | 4 |
| Power dissipation at 250 kSPS |  |  |  | 140 | mW | fSAMPLE = 250 kSPS | 4 |
| Power dissipation, standby |  |  |  | 40 | mW |  | 4 |
| Power dissipation, full shutdown (STBY low) |  |  |  | 315 | μW |  | 4 |
| VDD supply voltage | VDD | -5 |  | 16.5 | V | ±4 × VREF range, VDD = 10 V to 16.5 V | 4 |
| VSS supply voltage | VSS | -16.5 |  | -5 | V | ±4 × VREF range, VSS = −10 V to −16.5 V | 4 |
| Analog supply voltage | AVCC | 4.75 |  | 5.25 | V |  | 4 |
| Digital supply voltage | DVCC | 4.75 |  | 5.25 | V |  | 4 |
| Digital interface supply voltage | VDRIVE | 2.7 |  | 5.25 | V |  | 4 |
| Operating temperature range | TA | -40 |  | 85 | °C | B grade | 10 |
| VDD to AGND, DGND | VDD | -0.3 |  | 16.5 | V |  | 10 |
| VSS to AGND, DGND | VSS | -16.5 |  | 0.3 | V |  | 10 |
| AVCC to AGND, DGND | AVCC | -0.3 |  | 7 | V |  | 10 |
| DVCC to DGND, AGND | DVCC | -0.3 |  | 7 | V |  | 10 |
| AGND to DGND |  | -0.3 |  | 0.3 | V |  | 10 |
| Digital input voltage to DGND |  | -0.3 |  |  | V | Upper limit VDRIVE + 0.3 V | 10 |
| Digital output voltage to DGND |  | -0.3 |  |  | V | Upper limit VDRIVE + 0.3 V | 10 |
| REFIN/REFOUT to AGND |  | -0.3 |  |  | V | Upper limit AVCC + 0.3 V | 10 |
| Input current to any pin except supplies |  | -10 |  | 10 | mA |  | 10 |
| Storage temperature range |  | -65 |  | 150 | °C |  | 10 |
| Junction temperature |  |  |  | 150 | °C |  | 10 |
| Lead temperature, soldering |  |  |  | 240 | °C | 10 s to 30 s | 10 |
| Reflow peak temperature |  |  |  | 260 | °C |  | 10 |
| ESD rating |  |  |  | 1.5 | kV |  | 10 |
| Thermal resistance, junction-to-ambient (LQFP-64) | θJA |  | 45 |  | °C/W |  | 10 |
| Thermal resistance, junction-to-case (LQFP-64) | θJC |  | 11 |  | °C/W |  | 10 |
| Conversion time | tCONVERT |  |  | 3 | μs | VDRIVE = 4.75 V to 5.25 V | 9 |
| Quiet time before CONVST | tQUIET | 150 |  |  | ns | VDRIVE = 4.75 V to 5.25 V | 9 |
| Acquisition time | tACQ | 550 |  |  | ns | VDRIVE = 4.75 V to 5.25 V | 9 |
| CONVST pulse spacing | t10 | 25 |  |  | ns | VDRIVE = 4.75 V to 5.25 V | 9 |
| CONVST rising edge to BUSY rising edge delay | t1 |  |  | 60 | ns | VDRIVE = 4.75 V to 5.25 V | 9 |
| Wake-up time from STBY | tWAKE-UP |  |  | 2 | ms | VDRIVE = 4.75 V to 5.25 V | 9 |
| Serial clock frequency | fSCLK |  |  | 18 | MHz | VDRIVE = 4.75 V to 5.25 V | 9 |

## CAD (KiCad official)

- Symbol: `AD7656BSTZ-1`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `ad7656bstz-1-etched.step` / `ad7656bstz-1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7656bstz-1.step` / `ad7656bstz-1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885146837110784) (32 pp, sha256 `67071afe34b463ae`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad7656bstz-1-datasheet.pdf)