AD7656ABSTZ

Analog Devices · Analog To Digital Converters (ADCs) · LQFP-64(10x10)

AD7656ABSTZ from Analog Devices, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DB14/REFBUFEN/DIS	bidirectional	Data Bit 14 in parallel mode, and Reference Buffer Enable/Disable; acts as a three-state digital input/output when SER/PAR/SEL = 0.
2	DB13	bidirectional	Data Bit 13 three-state parallel I/O when SER/PAR/SEL = 0; tie to DGND when SER/PAR/SEL = 1.
3	DB12	bidirectional	Data Bit 12 three-state parallel I/O when SER/PAR/SEL = 0; tie to DGND when SER/PAR/SEL = 1.
4	DB11	bidirectional	Data Bit 11 three-state parallel output when SER/PAR/SEL = 0; tie to DGND when SER/PAR/SEL = 1.
5	DB10/DOUT C	bidirectional	Data Bit 10 parallel output when SER/PAR/SEL = 0; serial data output C when SER/PAR/SEL = 1 and SEL C = 1.
6	DB9/DOUT B	bidirectional	Data Bit 9 parallel output when SER/PAR/SEL = 0; serial data output B when SER/PAR/SEL = 1 and SEL B = 1.
7	DB8/DOUT A	bidirectional	Data Bit 8 parallel output when SER/PAR/SEL = 0; serial data output A when SER/PAR/SEL = 1 and SEL A = 1.
8	DGND	power_in	Digital ground reference for all digital circuitry; must not differ from AGND by more than 0.3 V, even transiently.
9	VDRIVE	power_in	Logic supply input that sets the interface voltage, specified at 2.7 V to 5.25 V; decouple with 10 µF and 100 nF.
10	DB7/HBEN/DCEN	bidirectional	Data Bit 7 in word mode, HBEN in byte mode, and DCEN daisy-chain enable in serial mode; tie DCEN to DGND when not daisy-chaining.
11	DB6/SCLK	input	Data Bit 6 three-state output when SER/PAR/SEL = 0; serial read clock input SCLK (maximum 18 MHz) when SER/PAR/SEL = 1.
12	DB5/DCIN A	bidirectional	Data Bit 5 parallel output when SER/PAR/SEL = 0; Daisy-Chain Input A when SER/PAR/SEL = 1 and DCEN = 1, otherwise tie to DGND.
13	DB4/DCIN B	bidirectional	Data Bit 4 parallel output when SER/PAR/SEL = 0; Daisy-Chain Input B when SER/PAR/SEL = 1 and DCEN = 1, otherwise tie to DGND.
14	DB3/DCIN C	bidirectional	Data Bit 3 parallel output when SER/PAR/SEL = 0; Daisy-Chain Input C when SER/PAR/SEL = 1 and DCEN = 1, otherwise tie to DGND.
15	DB2/SEL C	bidirectional	Data Bit 2 parallel output when SER/PAR/SEL = 0; SEL C serial configuration input when SER/PAR/SEL = 1 (1 enables DOUT C).
16	DB1/SEL B	bidirectional	Data Bit 1 parallel output when SER/PAR/SEL = 0; SEL B serial configuration input when SER/PAR/SEL = 1 (1 enables DOUT B).
17	DB0/SEL A	bidirectional	Data Bit 0 parallel output when SER/PAR/SEL = 0; SEL A serial configuration input that must be 1 in serial mode.
18	BUSY	output	Goes high when a conversion starts and stays high until the data is latched; do not start a new conversion while BUSY is high.
19	CS	input	Active-low chip select that frames parallel reads/writes and serial reads; output bus is enabled when CS and RD are low.
20	RD	input	Active-low read strobe that enables the parallel output bus with CS low; hold low in serial mode.
21	CONVST C	input	Conversion start input for simultaneous sampling of V5 and V6; a low-to-high edge starts the conversion.
22	CONVST B	input	Conversion start input for simultaneous sampling of V3 and V4; a low-to-high edge starts the conversion.
23	CONVST A	input	Conversion start input for simultaneous sampling of V1 and V2; a low-to-high edge starts the conversion.
24	STBY	input	Standby input for all six ADCs; high for normal operation and low for standby.
25	DGND	power_in	Digital ground reference; connect together with pin 8 to the system DGND plane.
26	DVCC	power_in	Digital power supply specified at 4.75 V to 5.25 V; keep within 0.3 V of AVCC and decouple with 10 µF and 100 nF.
27	RANGE	input	Input range select: logic 1 selects ±2 × VREF and logic 0 selects ±4 × VREF, sampled at the falling edge of BUSY in hardware mode.
28	RESET	input	Active-high reset that aborts any conversion and clears the internal register; a RESET pulse is required after power-up.
29	W/B	input	Word/byte select: logic low for 16-bit parallel word mode and logic high for byte mode; tie to DGND in serial mode.
30	VSS	power_in	Negative analog supply, specified from −6 V to −16.5 V; decouple with 10 µF and 100 nF.
31	VDD	power_in	Positive analog supply, specified from 6 V to 16.5 V; decouple with 10 µF and 100 nF.
32	AGND	power_in	Analog ground reference for all analog circuitry; connect all AGND pins to the system AGND plane.
33	V1	input	Single-ended bipolar analog input 1, with range set by the RANGE pin or the RNGC-RNGA control bits.
34	AVCC	power_in	Analog supply for the ADC cores, specified at 4.75 V to 5.25 V; decouple to AGND with 10 µF and 100 nF.
35	AVCC	power_in	Analog supply for the ADC cores, specified at 4.75 V to 5.25 V; decouple to AGND with 10 µF and 100 nF.
36	V2	input	Single-ended bipolar analog input 2, with range set by the RANGE pin or the RNGC-RNGA control bits.
37	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane.
38	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane.
39	V3	input	Single-ended bipolar analog input 3, with range set by the RANGE pin or the RNGC-RNGA control bits.
40	AVCC	power_in	Analog supply for the ADC cores, specified at 4.75 V to 5.25 V; decouple to AGND with 10 µF and 100 nF.
41	AVCC	power_in	Analog supply for the ADC cores, specified at 4.75 V to 5.25 V; decouple to AGND with 10 µF and 100 nF.
42	V4	input	Single-ended bipolar analog input 4, with range set by the RANGE pin or the RNGC-RNGA control bits.
43	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane.
44	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane.
45	V5	input	Single-ended bipolar analog input 5, with range set by the RANGE pin or the RNGC-RNGA control bits.
46	AVCC	power_in	Analog supply for the ADC cores, specified at 4.75 V to 5.25 V; decouple to AGND with 10 µF and 100 nF.
47	AVCC	power_in	Analog supply for the ADC cores, specified at 4.75 V to 5.25 V; decouple to AGND with 10 µF and 100 nF.
48	V6	input	Single-ended bipolar analog input 6, with range set by the RANGE pin or the RNGC-RNGA control bits.
49	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane.
50	AVCC	power_in	Analog supply for the ADC cores, specified at 4.75 V to 5.25 V; decouple to AGND with 10 µF and 100 nF.
51	REFIN/REFOUT	passive	On-chip reference output for external use, or external reference input when the internal reference is disabled; decouple with at least 10 µF when enabled.
52	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane.
53	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane.
54	REFCAPA	passive	Reference buffer decoupling pin for ADC pair A; decouple to AGND with 10 µF and 100 nF.
55	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane.
56	REFCAPB	passive	Reference buffer decoupling pin for ADC pair B; decouple to AGND with 10 µF and 100 nF.
57	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane.
58	REFCAPC	passive	Reference buffer decoupling pin for ADC pair C; decouple to AGND with 10 µF and 100 nF.
59	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane.
60	AVCC	power_in	Analog supply for the ADC cores, specified at 4.75 V to 5.25 V; decouple to AGND with 10 µF and 100 nF.
61	SER/PAR/SEL	input	Serial/parallel select: logic low selects the parallel interface and logic high selects the serial interface.
62	H/S SEL	input	Hardware/software select: logic 0 selects hardware mode with CONVST x choosing ADC pairs, and logic 1 selects software control-register mode.
63	WR/REFEN/DIS	input	Write strobe for control-register writes in software mode, or reference enable/disable when H/S SEL = 0.
64	DB15	bidirectional	Data Bit 15 three-state parallel I/O when SER/PAR/SEL = 0; tie to DGND when SER/PAR/SEL = 1.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LQFP-64(10x10)
Category	Data Converters
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Positive Full-Scale Error		-0.75		0.75	% FSR		3
Positive Full-Scale Error Matching		-0.35		0.35	% FSR		3
Bipolar Zero-Scale Error		-0.023		0.023	% FSR		3
Bipolar Zero-Scale Error Matching		-0.038		0.038	% FSR		3
Negative Full-Scale Error		-0.75		0.75	% FSR		3
Negative Full-Scale Error Matching		-0.35		0.35	% FSR		3
DC Leakage Current		-1		1	µA	Analog input	3
Reference Input Voltage Range		2.5		3	V		3
Reference Output Voltage		2.49		2.51	V		3
Reference Temperature Coefficient				25	ppm/°C		3
Reference Temperature Coefficient				6	ppm/°C		3
Input Current	IIN	-1		1	µA	Typically 10 nA, VIN = 0 V or VDRIVE	4
Floating State Leakage Current		-1		1	µA		4
Output Low Voltage	VOL			0.2	V	ISINK = 200 µA	4
VDD Range	VDD	6		16.5	V	For the 4 × VREF range, VDD = 11 V to 16.5 V	4
VSS Range	VSS	-16.5		-6	V	For the 4 × VREF range, VSS = −11 V to −16.5 V	4
AVCC	AVCC	4.75		5.25	V		4
DVCC	DVCC	4.75		5.25	V		4
VDRIVE	VDRIVE	2.7		5.25	V		4
Normal Mode (Static) supply current	ITOTAL			28	mA	AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V	4
Normal Mode (Operational) supply current	ITOTAL			26	mA	fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V	4
ISS (Operational)	ISS			0.25	mA	VSS = −16.5 V, fSAMPLE = 250 kSPS	4
IDD (Operational)	IDD			0.25	mA	VDD = 16.5 V, fSAMPLE = 250 kSPS	4
Partial Power-Down Mode supply current				7	mA	AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V	4
Full Power-Down Mode (STBY Pin) supply current				80	mA	SCLK on or off, AVCC = DVCC = VDRIVE = 5.25V, VDD = 16.5V, VSS = −16.5 V	4
Power Dissipation Normal Mode (Static)				143	mW	AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V	4
Power Dissipation Normal Mode (Operational)				140	mW	fSAMPLE = 250 kSPS	4
Power Dissipation Partial Power-Down Mode				35	mW	AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V	4
Power Dissipation Full Power-Down Mode (STBY Pin)				100	mW	AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V	4
Track-and-Hold Acquisition Time	tACQ	550			ns		5
Minimum quiet time between bus relinquish and start of next conversion	tQUIET	150			ns		5
CONVST x high to BUSY high	t1	60			ns		5
Minimum CONVST x low pulse	t10	25			ns		5
STBY rising edge to CONVST x rising edge	tWAKE-UP			2	ms		5
Partial power-down mode wake-up	tWAKE-UP			25	µs	Partial power-down mode	5
WR pulse width	t11	15			ns		5
CS to WR setup time	t12	0			ns		5
CS to WR hold time	t13	5			ns		5
Data setup time before WR rising edge	t14	5			ns		5
Data hold after WR rising edge	t15	5			ns		5
BUSY to RD delay	t2	0			ns		5
CS to RD setup time	t3	0			ns		5
CS to RD hold time	t4	0			ns		5
RD pulse width	t5	45			ns	VDRIVE < 4.75 V	5
RD pulse width	t5	36			ns	VDRIVE = 4.75 V to 5.25 V	5
Data access time after RD falling edge	t6			45	ns	VDRIVE < 4.75 V	5
Data access time after RD falling edge	t6			36	ns	VDRIVE = 4.75 V to 5.25 V	5
Data hold time after RD rising edge	t7	10			ns		5
Bus relinquish time after RD rising edge	t8			12	ns		5
Minimum time between reads	t9	6			ns		5
Frequency of serial read clock	fSCLK			18	MHz		5
Delay from CS until SDATA three-state disabled	t16			12	ns		5
Data access time after SCLK rising edge/CS falling edge	t17			22	ns	A buffer is used on the data output pins for this measurement	5
SCLK to data valid hold time after SCLK falling edge	t20	10			ns		5
CS rising edge to SDATA high impedance	t21			18	ns		5
VDD to AGND, DGND		0		16.5	V		6
VSS to AGND, DGND		-16.5		0	V		6
AVCC to AGND, DGND		-0.3		7	V		6
DVCC to DGND, AGND		-0.3		7	V		6
AGND to DGND		-0.3		0.3	V		6
Input Current to Any Pin Except Supplies		-10		10	mA		6
Operating Temperature Range	TA	-40		85	°C		6
Storage Temperature Range		-65		150	°C		6
Junction Temperature	TJ			150	°C		6
Thermal resistance junction-to-ambient	θJA		45		°C/W	64-Lead LQFP, 4-layer board	6
Thermal resistance junction-to-case	θJC		11		°C/W	64-Lead LQFP	6

CAD (KiCad official)

Symbol: AD7656ABSTZ
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: ad7656abstz-etched.step / ad7656abstz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7656abstz.step / ad7656abstz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (28 pp, sha256 44580dc51e815507, retrieved 2026-10-28, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# AD7656ABSTZ

**Analog Devices** · Analog To Digital Converters (ADCs) · LQFP-64(10x10)

AD7656ABSTZ from Analog Devices, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DB14/REFBUFEN/DIS | bidirectional | Data Bit 14 in parallel mode, and Reference Buffer Enable/Disable; acts as a three-state digital input/output when SER/PAR/SEL = 0. |
| 2 | DB13 | bidirectional | Data Bit 13 three-state parallel I/O when SER/PAR/SEL = 0; tie to DGND when SER/PAR/SEL = 1. |
| 3 | DB12 | bidirectional | Data Bit 12 three-state parallel I/O when SER/PAR/SEL = 0; tie to DGND when SER/PAR/SEL = 1. |
| 4 | DB11 | bidirectional | Data Bit 11 three-state parallel output when SER/PAR/SEL = 0; tie to DGND when SER/PAR/SEL = 1. |
| 5 | DB10/DOUT C | bidirectional | Data Bit 10 parallel output when SER/PAR/SEL = 0; serial data output C when SER/PAR/SEL = 1 and SEL C = 1. |
| 6 | DB9/DOUT B | bidirectional | Data Bit 9 parallel output when SER/PAR/SEL = 0; serial data output B when SER/PAR/SEL = 1 and SEL B = 1. |
| 7 | DB8/DOUT A | bidirectional | Data Bit 8 parallel output when SER/PAR/SEL = 0; serial data output A when SER/PAR/SEL = 1 and SEL A = 1. |
| 8 | DGND | power_in | Digital ground reference for all digital circuitry; must not differ from AGND by more than 0.3 V, even transiently. |
| 9 | VDRIVE | power_in | Logic supply input that sets the interface voltage, specified at 2.7 V to 5.25 V; decouple with 10 µF and 100 nF. |
| 10 | DB7/HBEN/DCEN | bidirectional | Data Bit 7 in word mode, HBEN in byte mode, and DCEN daisy-chain enable in serial mode; tie DCEN to DGND when not daisy-chaining. |
| 11 | DB6/SCLK | input | Data Bit 6 three-state output when SER/PAR/SEL = 0; serial read clock input SCLK (maximum 18 MHz) when SER/PAR/SEL = 1. |
| 12 | DB5/DCIN A | bidirectional | Data Bit 5 parallel output when SER/PAR/SEL = 0; Daisy-Chain Input A when SER/PAR/SEL = 1 and DCEN = 1, otherwise tie to DGND. |
| 13 | DB4/DCIN B | bidirectional | Data Bit 4 parallel output when SER/PAR/SEL = 0; Daisy-Chain Input B when SER/PAR/SEL = 1 and DCEN = 1, otherwise tie to DGND. |
| 14 | DB3/DCIN C | bidirectional | Data Bit 3 parallel output when SER/PAR/SEL = 0; Daisy-Chain Input C when SER/PAR/SEL = 1 and DCEN = 1, otherwise tie to DGND. |
| 15 | DB2/SEL C | bidirectional | Data Bit 2 parallel output when SER/PAR/SEL = 0; SEL C serial configuration input when SER/PAR/SEL = 1 (1 enables DOUT C). |
| 16 | DB1/SEL B | bidirectional | Data Bit 1 parallel output when SER/PAR/SEL = 0; SEL B serial configuration input when SER/PAR/SEL = 1 (1 enables DOUT B). |
| 17 | DB0/SEL A | bidirectional | Data Bit 0 parallel output when SER/PAR/SEL = 0; SEL A serial configuration input that must be 1 in serial mode. |
| 18 | BUSY | output | Goes high when a conversion starts and stays high until the data is latched; do not start a new conversion while BUSY is high. |
| 19 | CS | input | Active-low chip select that frames parallel reads/writes and serial reads; output bus is enabled when CS and RD are low. |
| 20 | RD | input | Active-low read strobe that enables the parallel output bus with CS low; hold low in serial mode. |
| 21 | CONVST C | input | Conversion start input for simultaneous sampling of V5 and V6; a low-to-high edge starts the conversion. |
| 22 | CONVST B | input | Conversion start input for simultaneous sampling of V3 and V4; a low-to-high edge starts the conversion. |
| 23 | CONVST A | input | Conversion start input for simultaneous sampling of V1 and V2; a low-to-high edge starts the conversion. |
| 24 | STBY | input | Standby input for all six ADCs; high for normal operation and low for standby. |
| 25 | DGND | power_in | Digital ground reference; connect together with pin 8 to the system DGND plane. |
| 26 | DVCC | power_in | Digital power supply specified at 4.75 V to 5.25 V; keep within 0.3 V of AVCC and decouple with 10 µF and 100 nF. |
| 27 | RANGE | input | Input range select: logic 1 selects ±2 × VREF and logic 0 selects ±4 × VREF, sampled at the falling edge of BUSY in hardware mode. |
| 28 | RESET | input | Active-high reset that aborts any conversion and clears the internal register; a RESET pulse is required after power-up. |
| 29 | W/B | input | Word/byte select: logic low for 16-bit parallel word mode and logic high for byte mode; tie to DGND in serial mode. |
| 30 | VSS | power_in | Negative analog supply, specified from −6 V to −16.5 V; decouple with 10 µF and 100 nF. |
| 31 | VDD | power_in | Positive analog supply, specified from 6 V to 16.5 V; decouple with 10 µF and 100 nF. |
| 32 | AGND | power_in | Analog ground reference for all analog circuitry; connect all AGND pins to the system AGND plane. |
| 33 | V1 | input | Single-ended bipolar analog input 1, with range set by the RANGE pin or the RNGC-RNGA control bits. |
| 34 | AVCC | power_in | Analog supply for the ADC cores, specified at 4.75 V to 5.25 V; decouple to AGND with 10 µF and 100 nF. |
| 35 | AVCC | power_in | Analog supply for the ADC cores, specified at 4.75 V to 5.25 V; decouple to AGND with 10 µF and 100 nF. |
| 36 | V2 | input | Single-ended bipolar analog input 2, with range set by the RANGE pin or the RNGC-RNGA control bits. |
| 37 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane. |
| 38 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane. |
| 39 | V3 | input | Single-ended bipolar analog input 3, with range set by the RANGE pin or the RNGC-RNGA control bits. |
| 40 | AVCC | power_in | Analog supply for the ADC cores, specified at 4.75 V to 5.25 V; decouple to AGND with 10 µF and 100 nF. |
| 41 | AVCC | power_in | Analog supply for the ADC cores, specified at 4.75 V to 5.25 V; decouple to AGND with 10 µF and 100 nF. |
| 42 | V4 | input | Single-ended bipolar analog input 4, with range set by the RANGE pin or the RNGC-RNGA control bits. |
| 43 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane. |
| 44 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane. |
| 45 | V5 | input | Single-ended bipolar analog input 5, with range set by the RANGE pin or the RNGC-RNGA control bits. |
| 46 | AVCC | power_in | Analog supply for the ADC cores, specified at 4.75 V to 5.25 V; decouple to AGND with 10 µF and 100 nF. |
| 47 | AVCC | power_in | Analog supply for the ADC cores, specified at 4.75 V to 5.25 V; decouple to AGND with 10 µF and 100 nF. |
| 48 | V6 | input | Single-ended bipolar analog input 6, with range set by the RANGE pin or the RNGC-RNGA control bits. |
| 49 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane. |
| 50 | AVCC | power_in | Analog supply for the ADC cores, specified at 4.75 V to 5.25 V; decouple to AGND with 10 µF and 100 nF. |
| 51 | REFIN/REFOUT | passive | On-chip reference output for external use, or external reference input when the internal reference is disabled; decouple with at least 10 µF when enabled. |
| 52 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane. |
| 53 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane. |
| 54 | REFCAPA | passive | Reference buffer decoupling pin for ADC pair A; decouple to AGND with 10 µF and 100 nF. |
| 55 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane. |
| 56 | REFCAPB | passive | Reference buffer decoupling pin for ADC pair B; decouple to AGND with 10 µF and 100 nF. |
| 57 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane. |
| 58 | REFCAPC | passive | Reference buffer decoupling pin for ADC pair C; decouple to AGND with 10 µF and 100 nF. |
| 59 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane. |
| 60 | AVCC | power_in | Analog supply for the ADC cores, specified at 4.75 V to 5.25 V; decouple to AGND with 10 µF and 100 nF. |
| 61 | SER/PAR/SEL | input | Serial/parallel select: logic low selects the parallel interface and logic high selects the serial interface. |
| 62 | H/S SEL | input | Hardware/software select: logic 0 selects hardware mode with CONVST x choosing ADC pairs, and logic 1 selects software control-register mode. |
| 63 | WR/REFEN/DIS | input | Write strobe for control-register writes in software mode, or reference enable/disable when H/S SEL = 0. |
| 64 | DB15 | bidirectional | Data Bit 15 three-state parallel I/O when SER/PAR/SEL = 0; tie to DGND when SER/PAR/SEL = 1. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LQFP-64(10x10) |
| Category | Data Converters |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Positive Full-Scale Error |  | -0.75 |  | 0.75 | % FSR |  | 3 |
| Positive Full-Scale Error Matching |  | -0.35 |  | 0.35 | % FSR |  | 3 |
| Bipolar Zero-Scale Error |  | -0.023 |  | 0.023 | % FSR |  | 3 |
| Bipolar Zero-Scale Error Matching |  | -0.038 |  | 0.038 | % FSR |  | 3 |
| Negative Full-Scale Error |  | -0.75 |  | 0.75 | % FSR |  | 3 |
| Negative Full-Scale Error Matching |  | -0.35 |  | 0.35 | % FSR |  | 3 |
| DC Leakage Current |  | -1 |  | 1 | µA | Analog input | 3 |
| Reference Input Voltage Range |  | 2.5 |  | 3 | V |  | 3 |
| Reference Output Voltage |  | 2.49 |  | 2.51 | V |  | 3 |
| Reference Temperature Coefficient |  |  |  | 25 | ppm/°C |  | 3 |
| Reference Temperature Coefficient |  |  |  | 6 | ppm/°C |  | 3 |
| Input Current | IIN | -1 |  | 1 | µA | Typically 10 nA, VIN = 0 V or VDRIVE | 4 |
| Floating State Leakage Current |  | -1 |  | 1 | µA |  | 4 |
| Output Low Voltage | VOL |  |  | 0.2 | V | ISINK = 200 µA | 4 |
| VDD Range | VDD | 6 |  | 16.5 | V | For the 4 × VREF range, VDD = 11 V to 16.5 V | 4 |
| VSS Range | VSS | -16.5 |  | -6 | V | For the 4 × VREF range, VSS = −11 V to −16.5 V | 4 |
| AVCC | AVCC | 4.75 |  | 5.25 | V |  | 4 |
| DVCC | DVCC | 4.75 |  | 5.25 | V |  | 4 |
| VDRIVE | VDRIVE | 2.7 |  | 5.25 | V |  | 4 |
| Normal Mode (Static) supply current | ITOTAL |  |  | 28 | mA | AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V | 4 |
| Normal Mode (Operational) supply current | ITOTAL |  |  | 26 | mA | fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V | 4 |
| ISS (Operational) | ISS |  |  | 0.25 | mA | VSS = −16.5 V, fSAMPLE = 250 kSPS | 4 |
| IDD (Operational) | IDD |  |  | 0.25 | mA | VDD = 16.5 V, fSAMPLE = 250 kSPS | 4 |
| Partial Power-Down Mode supply current |  |  |  | 7 | mA | AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V | 4 |
| Full Power-Down Mode (STBY Pin) supply current |  |  |  | 80 | mA | SCLK on or off, AVCC = DVCC = VDRIVE = 5.25V, VDD = 16.5V, VSS = −16.5 V | 4 |
| Power Dissipation Normal Mode (Static) |  |  |  | 143 | mW | AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V | 4 |
| Power Dissipation Normal Mode (Operational) |  |  |  | 140 | mW | fSAMPLE = 250 kSPS | 4 |
| Power Dissipation Partial Power-Down Mode |  |  |  | 35 | mW | AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V | 4 |
| Power Dissipation Full Power-Down Mode (STBY Pin) |  |  |  | 100 | mW | AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V | 4 |
| Track-and-Hold Acquisition Time | tACQ | 550 |  |  | ns |  | 5 |
| Minimum quiet time between bus relinquish and start of next conversion | tQUIET | 150 |  |  | ns |  | 5 |
| CONVST x high to BUSY high | t1 | 60 |  |  | ns |  | 5 |
| Minimum CONVST x low pulse | t10 | 25 |  |  | ns |  | 5 |
| STBY rising edge to CONVST x rising edge | tWAKE-UP |  |  | 2 | ms |  | 5 |
| Partial power-down mode wake-up | tWAKE-UP |  |  | 25 | µs | Partial power-down mode | 5 |
| WR pulse width | t11 | 15 |  |  | ns |  | 5 |
| CS to WR setup time | t12 | 0 |  |  | ns |  | 5 |
| CS to WR hold time | t13 | 5 |  |  | ns |  | 5 |
| Data setup time before WR rising edge | t14 | 5 |  |  | ns |  | 5 |
| Data hold after WR rising edge | t15 | 5 |  |  | ns |  | 5 |
| BUSY to RD delay | t2 | 0 |  |  | ns |  | 5 |
| CS to RD setup time | t3 | 0 |  |  | ns |  | 5 |
| CS to RD hold time | t4 | 0 |  |  | ns |  | 5 |
| RD pulse width | t5 | 45 |  |  | ns | VDRIVE < 4.75 V | 5 |
| RD pulse width | t5 | 36 |  |  | ns | VDRIVE = 4.75 V to 5.25 V | 5 |
| Data access time after RD falling edge | t6 |  |  | 45 | ns | VDRIVE < 4.75 V | 5 |
| Data access time after RD falling edge | t6 |  |  | 36 | ns | VDRIVE = 4.75 V to 5.25 V | 5 |
| Data hold time after RD rising edge | t7 | 10 |  |  | ns |  | 5 |
| Bus relinquish time after RD rising edge | t8 |  |  | 12 | ns |  | 5 |
| Minimum time between reads | t9 | 6 |  |  | ns |  | 5 |
| Frequency of serial read clock | fSCLK |  |  | 18 | MHz |  | 5 |
| Delay from CS until SDATA three-state disabled | t16 |  |  | 12 | ns |  | 5 |
| Data access time after SCLK rising edge/CS falling edge | t17 |  |  | 22 | ns | A buffer is used on the data output pins for this measurement | 5 |
| SCLK to data valid hold time after SCLK falling edge | t20 | 10 |  |  | ns |  | 5 |
| CS rising edge to SDATA high impedance | t21 |  |  | 18 | ns |  | 5 |
| VDD to AGND, DGND |  | 0 |  | 16.5 | V |  | 6 |
| VSS to AGND, DGND |  | -16.5 |  | 0 | V |  | 6 |
| AVCC to AGND, DGND |  | -0.3 |  | 7 | V |  | 6 |
| DVCC to DGND, AGND |  | -0.3 |  | 7 | V |  | 6 |
| AGND to DGND |  | -0.3 |  | 0.3 | V |  | 6 |
| Input Current to Any Pin Except Supplies |  | -10 |  | 10 | mA |  | 6 |
| Operating Temperature Range | TA | -40 |  | 85 | °C |  | 6 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 6 |
| Junction Temperature | TJ |  |  | 150 | °C |  | 6 |
| Thermal resistance junction-to-ambient | θJA |  | 45 |  | °C/W | 64-Lead LQFP, 4-layer board | 6 |
| Thermal resistance junction-to-case | θJC |  | 11 |  | °C/W | 64-Lead LQFP | 6 |

## CAD (KiCad official)

- Symbol: `AD7656ABSTZ`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `ad7656abstz-etched.step` / `ad7656abstz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7656abstz.step` / `ad7656abstz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7656A.pdf) (28 pp, sha256 `44580dc51e815507`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad7656abstz-datasheet.pdf)