AD7656A-1BSTZ

Analog Devices · Analog To Digital Converters (ADCs) · LQFP-64(10x10)

AD7656A-1BSTZ from Analog Devices, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DB14/REFBUFEN/DIS	bidirectional	Data Bit 14 and Reference Buffer Enable/Disable; when SER/PAR/SEL = 0 it acts as a three-state digital input/output pin.
2	DB13	bidirectional	Data Bit 13; in parallel mode it is a three-state I/O used for the conversion result and control register writes, and must be tied to DGND when SER/PAR/SEL = 1.
3	DB12	bidirectional	Data Bit 12; in parallel mode it is a three-state I/O used for the conversion result and control register writes, and must be tied to DGND when SER/PAR/SEL = 1.
4	DB11	bidirectional	Data Bit 11; a three-state parallel digital output in parallel mode, and must be tied to DGND when SER/PAR/SEL = 1.
5	DB10/DOUT C	bidirectional	Data Bit 10 in parallel mode; serial data output C when SER/PAR/SEL = 1 and SEL C = 1.
6	DB9/DOUT B	bidirectional	Data Bit 9 in parallel mode; serial data output B when SER/PAR/SEL = 1 and SEL B = 1.
7	DB8/DOUT A	bidirectional	Data Bit 8 in parallel mode; serial data output A when SER/PAR/SEL = 1 and SEL A = 1.
8	DGND	power_in	Digital ground reference for all digital circuitry; must not differ from AGND by more than 0.3 V, even transiently.
9	VDRIVE	power_in	Logic power supply input that sets the interface operating voltage, specified at 2.7 V to 5.25 V.
10	DB7/HBEN/DCEN	bidirectional	Data Bit 7 in word mode, HBEN in byte mode, and DCEN in serial mode; tie to DGND in serial mode when daisy-chain is not used.
11	DB6/SCLK	bidirectional	Data Bit 6 in parallel mode; serial read clock input SCLK when SER/PAR/SEL = 1.
12	DB5/DCIN A	bidirectional	Data Bit 5 in parallel mode; Daisy-Chain Input A when SER/PAR/SEL = 1 and DCEN = 1, otherwise tie to DGND in serial mode.
13	DB4/DCIN B	bidirectional	Data Bit 4 in parallel mode; Daisy-Chain Input B when SER/PAR/SEL = 1 and DCEN = 1, otherwise tie to DGND in serial mode.
14	DB3/DCIN C	bidirectional	Data Bit 3 in parallel mode; Daisy-Chain Input C when SER/PAR/SEL = 1 and DCEN = 1, otherwise tie to DGND in serial mode.
15	DB2/SEL C	bidirectional	Data Bit 2 in parallel mode; SEL C serial configuration input, where 1 enables DOUT C and unused DOUT pins are left unconnected.
16	DB1/SEL B	bidirectional	Data Bit 1 in parallel mode; SEL B serial configuration input, where 1 enables DOUT B and unused DOUT pins are left unconnected.
17	DB0/SEL A	bidirectional	Data Bit 0 in parallel mode; SEL A serial configuration input, which must always be set to 1 when the serial interface is selected.
18	BUSY	output	Busy output that goes high when a conversion starts and stays high until conversion data is latched; CONVST edges are ignored while BUSY is high.
19	CS	input	Active-low chip select that frames parallel reads and writes or the serial read transfer.
20	RD	input	Active-low read strobe for parallel reads; must be held low when the serial interface is selected.
21	CONVST C	input	Conversion start input that initiates simultaneous conversions on V5 and V6 on its rising edge.
22	CONVST B	input	Conversion start input that initiates simultaneous conversions on V3 and V4 on its rising edge.
23	CONVST A	input	Conversion start input that initiates simultaneous conversions on V1 and V2 on its rising edge.
24	STBY	input	Standby mode input that is high for normal operation and low to put all six ADCs into standby.
25	DGND	power_in	Digital ground reference for all digital circuitry; must not differ from AGND by more than 0.3 V, even transiently.
26	DVCC	power_in	Digital power supply specified at 4.75 V to 5.25 V, to be kept within 0.3 V of AVCC and decoupled to DGND with 1 µF.
27	RANGE	input	Analog input range select sampled at the falling edge of BUSY: logic 1 selects ±2 × VREF and logic 0 selects ±4 × VREF in hardware mode.
28	RESET	input	Reset input where a high pulse, typically 100 ns wide, resets the device and should be applied once after power-up.
29	W/B	input	Word/Byte input where logic low selects 16-bit word transfers on DB15 to DB0 and logic high selects byte mode; tie to DGND for serial mode.
30	VSS	power_in	Negative analog supply for the analog input section, specified at −6 V to −16.5 V.
31	VDD	power_in	Positive analog supply for the analog input section, specified at 6 V to 16.5 V.
32	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND.
33	V1	input	Single-ended analog input 1 with range set by the RANGE pin in hardware mode or by the RNGA bit in software mode.
34	AVCC	power_in	Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC.
35	AVCC	power_in	Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC.
36	V2	input	Single-ended analog input 2 with range set by the RANGE pin in hardware mode or by the RNGA bit in software mode.
37	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND.
38	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND.
39	V3	input	Single-ended analog input 3 with range set by the RANGE pin in hardware mode or by the RNGB bit in software mode.
40	AVCC	power_in	Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC.
41	AVCC	power_in	Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC.
42	V4	input	Single-ended analog input 4 with range set by the RANGE pin in hardware mode or by the RNGB bit in software mode.
43	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND.
44	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND.
45	V5	input	Single-ended analog input 5 with range set by the RANGE pin in hardware mode or by the RNGC bit in software mode.
46	AVCC	power_in	Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC.
47	AVCC	power_in	Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC.
48	V6	input	Single-ended analog input 6 with range set by the RANGE pin in hardware mode or by the RNGC bit in software mode.
49	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND.
50	AVCC	power_in	Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC.
51	REFIN/REFOUT	bidirectional	Reference input or output; the on-chip reference is available here, and when it is enabled the pin needs at least a 1 µF decoupling capacitor.
52	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND.
53	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND.
54	REFCAPA	passive	Reference buffer decoupling pin for ADC pair A, to be decoupled to AGND with a 1 µF capacitor.
55	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND.
56	REFCAPB	passive	Reference buffer decoupling pin for ADC pair B, to be decoupled to AGND with a 1 µF capacitor.
57	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND.
58	REFCAPC	passive	Reference buffer decoupling pin for ADC pair C, to be decoupled to AGND with a 1 µF capacitor.
59	AGND	power_in	Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND.
60	AVCC	power_in	Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC.
61	SER/PAR SEL	input	Serial/parallel selection input where logic low selects the parallel interface and logic high selects the serial interface.
62	H/S SEL	input	Hardware/software select input where logic 0 selects CONVST-controlled hardware mode and logic 1 selects control-register software mode.
63	WR/REFEN/DIS	input	Write strobe in software mode with CS, and reference enable/disable in hardware mode where logic 1 enables the internal reference.
64	DB15	bidirectional	Data Bit 15; in parallel mode it is a three-state I/O used for the conversion result and control register writes, and must be tied to DGND when SER/PAR/SEL = 1.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LQFP-64(10x10)
Category	Data Converters
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Signal-to-Noise + Distortion (SINAD)	SINAD	88			dB	fIN = 10 kHz sine wave	3
Signal-to-Noise Ratio (SNR)	SNR	88			dB	fIN = 10 kHz sine wave	3
Total Harmonic Distortion (THD)	THD			-90	dB	fIN = 10 kHz sine wave	3
Peak Harmonic or Spurious Noise (SFDR)	SFDR			-100	dB	fIN = 10 kHz sine wave	3
Integral Nonlinearity	INL	-3		3	LSB		3
Positive Full-Scale Error		-0.8	0.381	0.8	% FSR		3
Positive Full-Scale Error Matching		-0.35		0.35	% FSR		3
Bipolar Zero-Scale Error		-0.048	0.0137	0.048	% FSR		3
Bipolar Zero-Scale Error Matching		-0.038		0.038	% FSR		3
Negative Full-Scale Error		-0.8	0.381	0.8	% FSR		3
Negative Full-Scale Error Matching		-0.35		0.35	% FSR		3
DC Leakage Current (analog input)		-1		1	µA		3
Reference Input Voltage Range		2.5		3	V		3
Reference Output Voltage		2.49		2.51	V		3
DC Leakage Current (reference input)		-1		1	µA		3
Reference Temperature Coefficient				25	ppm/°C		3
Input Current (IIN)	IIN	-10		10	µA	Typically 10 nA, VIN = 0 V or VDRIVE	4
Output Low Voltage (VOL)	VOL			0.2	V	ISINK = 200 µA	4
Floating-State Leakage Current		-10		10	µA		4
Normal Mode (Static) Supply Current	ITOTAL			18	mA	Digital inputs = 0 V or VDRIVE; AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V	4
Normal Mode (Operational) Supply Current	ITOTAL			26	mA	fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V	4
ISS (Operational)	ISS			0.25	mA	VSS = −16.5 V, fSAMPLE = 250 kSPS	4
IDD (Operational)	IDD			0.25	mA	VDD = 16.5 V, fSAMPLE = 250 kSPS	4
Partial Power-Down Mode Current				7	mA	AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V	4
Full Power-Down Mode Current (STBY pin)				60	µA	SCLK on or off, AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V	4
Full Power-Down Mode Power Dissipation (STBY pin)				315	µW	AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V	4
VDD Range	VDD	6		16.5	V	For the ±4 × VREF range, VDD = 11 V to 16.5 V	4
VSS Range	VSS	-16.5		-6	V	For the ±4 × VREF range, VSS = −11 V to −16.5 V	4
AVCC Supply Voltage	AVCC	4.75		5.25	V		4
DVCC Supply Voltage	DVCC	4.75		5.25	V		4
VDRIVE Supply Voltage	VDRIVE	2.7		5.25	V		4
Minimum VDD/VSS Supply Voltage for ±4 × VREF Input Range		11			V	Analog input range ±4 × VREF, reference voltage 2.5 V	15
VDD to AGND, DGND		0		16.5	V		6
VSS to AGND, DGND		-16.5		0	V		6
AVCC to AGND, DGND		-0.3		7	V		6
DVCC to DGND, AGND		-0.3		7	V		6
AGND to DGND		-0.3		0.3	V		6
Input Current to Any Pin Except Supplies		-10		10	mA		6
Operating Temperature Range	TA	-40		85	°C		6
Storage Temperature Range		-65		150	°C		6
Junction Temperature				150	°C		6
Conversion Time (internal clock)	tCONV		3		µs	Conversion time, internal clock	5
Minimum Quiet Time Between Bus Relinquish and Start of Next Conversion	tQUIET	150			ns		5
Acquisition Time	tACQ	550			ns		5
CONVST x High to BUSY High	t1			60	ns		5
STBY Rising Edge to CONVST x Rising Edge (wake-up)	tWAKE-UP			2	ms	Not shown in figures	5
BUSY to RD Delay	t2	0			ns		5
RD Pulse Width	t5	45			ns	VDRIVE < 4.75 V	5
RD Pulse Width	t5	36			ns	VDRIVE = 4.75 V to 5.25 V	5
Data Access Time after RD Falling Edge	t6			45	ns	VDRIVE < 4.75 V	5
Data Access Time after RD Falling Edge	t6			36	ns	VDRIVE = 4.75 V to 5.25 V	5
Bus Relinquish Time after RD Rising Edge	t8			12	ns		5
WR Pulse Width	t11	15			ns		5
Frequency of Serial Read Clock	fSCLK			18	MHz		5
Delay from CS until DOUT x Three-State Disabled	t16			12	ns		5
Data Access Time after SCLK Rising Edge/CS Falling Edge	t17			22	ns		5
CS Rising Edge to DOUT x High Impedance	t21			18	ns		5
Thermal Resistance Junction-to-Ambient (64-Lead LQFP)	θJA		45		°C/W	Device soldered in 4-layer circuit board	6
Thermal Resistance Junction-to-Case (64-Lead LQFP)	θJC		11		°C/W		6

CAD (KiCad official)

Symbol: AD7656A-1BSTZ
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: ad7656a-1bstz-etched.step / ad7656a-1bstz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7656a-1bstz.step / ad7656a-1bstz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (28 pp, sha256 1cf58573a1cb97c1, retrieved 2026-10-28, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# AD7656A-1BSTZ

**Analog Devices** · Analog To Digital Converters (ADCs) · LQFP-64(10x10)

AD7656A-1BSTZ from Analog Devices, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DB14/REFBUFEN/DIS | bidirectional | Data Bit 14 and Reference Buffer Enable/Disable; when SER/PAR/SEL = 0 it acts as a three-state digital input/output pin. |
| 2 | DB13 | bidirectional | Data Bit 13; in parallel mode it is a three-state I/O used for the conversion result and control register writes, and must be tied to DGND when SER/PAR/SEL = 1. |
| 3 | DB12 | bidirectional | Data Bit 12; in parallel mode it is a three-state I/O used for the conversion result and control register writes, and must be tied to DGND when SER/PAR/SEL = 1. |
| 4 | DB11 | bidirectional | Data Bit 11; a three-state parallel digital output in parallel mode, and must be tied to DGND when SER/PAR/SEL = 1. |
| 5 | DB10/DOUT C | bidirectional | Data Bit 10 in parallel mode; serial data output C when SER/PAR/SEL = 1 and SEL C = 1. |
| 6 | DB9/DOUT B | bidirectional | Data Bit 9 in parallel mode; serial data output B when SER/PAR/SEL = 1 and SEL B = 1. |
| 7 | DB8/DOUT A | bidirectional | Data Bit 8 in parallel mode; serial data output A when SER/PAR/SEL = 1 and SEL A = 1. |
| 8 | DGND | power_in | Digital ground reference for all digital circuitry; must not differ from AGND by more than 0.3 V, even transiently. |
| 9 | VDRIVE | power_in | Logic power supply input that sets the interface operating voltage, specified at 2.7 V to 5.25 V. |
| 10 | DB7/HBEN/DCEN | bidirectional | Data Bit 7 in word mode, HBEN in byte mode, and DCEN in serial mode; tie to DGND in serial mode when daisy-chain is not used. |
| 11 | DB6/SCLK | bidirectional | Data Bit 6 in parallel mode; serial read clock input SCLK when SER/PAR/SEL = 1. |
| 12 | DB5/DCIN A | bidirectional | Data Bit 5 in parallel mode; Daisy-Chain Input A when SER/PAR/SEL = 1 and DCEN = 1, otherwise tie to DGND in serial mode. |
| 13 | DB4/DCIN B | bidirectional | Data Bit 4 in parallel mode; Daisy-Chain Input B when SER/PAR/SEL = 1 and DCEN = 1, otherwise tie to DGND in serial mode. |
| 14 | DB3/DCIN C | bidirectional | Data Bit 3 in parallel mode; Daisy-Chain Input C when SER/PAR/SEL = 1 and DCEN = 1, otherwise tie to DGND in serial mode. |
| 15 | DB2/SEL C | bidirectional | Data Bit 2 in parallel mode; SEL C serial configuration input, where 1 enables DOUT C and unused DOUT pins are left unconnected. |
| 16 | DB1/SEL B | bidirectional | Data Bit 1 in parallel mode; SEL B serial configuration input, where 1 enables DOUT B and unused DOUT pins are left unconnected. |
| 17 | DB0/SEL A | bidirectional | Data Bit 0 in parallel mode; SEL A serial configuration input, which must always be set to 1 when the serial interface is selected. |
| 18 | BUSY | output | Busy output that goes high when a conversion starts and stays high until conversion data is latched; CONVST edges are ignored while BUSY is high. |
| 19 | CS | input | Active-low chip select that frames parallel reads and writes or the serial read transfer. |
| 20 | RD | input | Active-low read strobe for parallel reads; must be held low when the serial interface is selected. |
| 21 | CONVST C | input | Conversion start input that initiates simultaneous conversions on V5 and V6 on its rising edge. |
| 22 | CONVST B | input | Conversion start input that initiates simultaneous conversions on V3 and V4 on its rising edge. |
| 23 | CONVST A | input | Conversion start input that initiates simultaneous conversions on V1 and V2 on its rising edge. |
| 24 | STBY | input | Standby mode input that is high for normal operation and low to put all six ADCs into standby. |
| 25 | DGND | power_in | Digital ground reference for all digital circuitry; must not differ from AGND by more than 0.3 V, even transiently. |
| 26 | DVCC | power_in | Digital power supply specified at 4.75 V to 5.25 V, to be kept within 0.3 V of AVCC and decoupled to DGND with 1 µF. |
| 27 | RANGE | input | Analog input range select sampled at the falling edge of BUSY: logic 1 selects ±2 × VREF and logic 0 selects ±4 × VREF in hardware mode. |
| 28 | RESET | input | Reset input where a high pulse, typically 100 ns wide, resets the device and should be applied once after power-up. |
| 29 | W/B | input | Word/Byte input where logic low selects 16-bit word transfers on DB15 to DB0 and logic high selects byte mode; tie to DGND for serial mode. |
| 30 | VSS | power_in | Negative analog supply for the analog input section, specified at −6 V to −16.5 V. |
| 31 | VDD | power_in | Positive analog supply for the analog input section, specified at 6 V to 16.5 V. |
| 32 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND. |
| 33 | V1 | input | Single-ended analog input 1 with range set by the RANGE pin in hardware mode or by the RNGA bit in software mode. |
| 34 | AVCC | power_in | Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC. |
| 35 | AVCC | power_in | Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC. |
| 36 | V2 | input | Single-ended analog input 2 with range set by the RANGE pin in hardware mode or by the RNGA bit in software mode. |
| 37 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND. |
| 38 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND. |
| 39 | V3 | input | Single-ended analog input 3 with range set by the RANGE pin in hardware mode or by the RNGB bit in software mode. |
| 40 | AVCC | power_in | Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC. |
| 41 | AVCC | power_in | Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC. |
| 42 | V4 | input | Single-ended analog input 4 with range set by the RANGE pin in hardware mode or by the RNGB bit in software mode. |
| 43 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND. |
| 44 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND. |
| 45 | V5 | input | Single-ended analog input 5 with range set by the RANGE pin in hardware mode or by the RNGC bit in software mode. |
| 46 | AVCC | power_in | Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC. |
| 47 | AVCC | power_in | Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC. |
| 48 | V6 | input | Single-ended analog input 6 with range set by the RANGE pin in hardware mode or by the RNGC bit in software mode. |
| 49 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND. |
| 50 | AVCC | power_in | Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC. |
| 51 | REFIN/REFOUT | bidirectional | Reference input or output; the on-chip reference is available here, and when it is enabled the pin needs at least a 1 µF decoupling capacitor. |
| 52 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND. |
| 53 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND. |
| 54 | REFCAPA | passive | Reference buffer decoupling pin for ADC pair A, to be decoupled to AGND with a 1 µF capacitor. |
| 55 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND. |
| 56 | REFCAPB | passive | Reference buffer decoupling pin for ADC pair B, to be decoupled to AGND with a 1 µF capacitor. |
| 57 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND. |
| 58 | REFCAPC | passive | Reference buffer decoupling pin for ADC pair C, to be decoupled to AGND with a 1 µF capacitor. |
| 59 | AGND | power_in | Analog ground reference for all analog circuitry; connect to the system AGND plane and keep within 0.3 V of DGND. |
| 60 | AVCC | power_in | Analog supply for the ADC cores, specified at 4.75 V to 5.25 V and kept within 0.3 V of DVCC. |
| 61 | SER/PAR SEL | input | Serial/parallel selection input where logic low selects the parallel interface and logic high selects the serial interface. |
| 62 | H/S SEL | input | Hardware/software select input where logic 0 selects CONVST-controlled hardware mode and logic 1 selects control-register software mode. |
| 63 | WR/REFEN/DIS | input | Write strobe in software mode with CS, and reference enable/disable in hardware mode where logic 1 enables the internal reference. |
| 64 | DB15 | bidirectional | Data Bit 15; in parallel mode it is a three-state I/O used for the conversion result and control register writes, and must be tied to DGND when SER/PAR/SEL = 1. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LQFP-64(10x10) |
| Category | Data Converters |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Signal-to-Noise + Distortion (SINAD) | SINAD | 88 |  |  | dB | fIN = 10 kHz sine wave | 3 |
| Signal-to-Noise Ratio (SNR) | SNR | 88 |  |  | dB | fIN = 10 kHz sine wave | 3 |
| Total Harmonic Distortion (THD) | THD |  |  | -90 | dB | fIN = 10 kHz sine wave | 3 |
| Peak Harmonic or Spurious Noise (SFDR) | SFDR |  |  | -100 | dB | fIN = 10 kHz sine wave | 3 |
| Integral Nonlinearity | INL | -3 |  | 3 | LSB |  | 3 |
| Positive Full-Scale Error |  | -0.8 | 0.381 | 0.8 | % FSR |  | 3 |
| Positive Full-Scale Error Matching |  | -0.35 |  | 0.35 | % FSR |  | 3 |
| Bipolar Zero-Scale Error |  | -0.048 | 0.0137 | 0.048 | % FSR |  | 3 |
| Bipolar Zero-Scale Error Matching |  | -0.038 |  | 0.038 | % FSR |  | 3 |
| Negative Full-Scale Error |  | -0.8 | 0.381 | 0.8 | % FSR |  | 3 |
| Negative Full-Scale Error Matching |  | -0.35 |  | 0.35 | % FSR |  | 3 |
| DC Leakage Current (analog input) |  | -1 |  | 1 | µA |  | 3 |
| Reference Input Voltage Range |  | 2.5 |  | 3 | V |  | 3 |
| Reference Output Voltage |  | 2.49 |  | 2.51 | V |  | 3 |
| DC Leakage Current (reference input) |  | -1 |  | 1 | µA |  | 3 |
| Reference Temperature Coefficient |  |  |  | 25 | ppm/°C |  | 3 |
| Input Current (IIN) | IIN | -10 |  | 10 | µA | Typically 10 nA, VIN = 0 V or VDRIVE | 4 |
| Output Low Voltage (VOL) | VOL |  |  | 0.2 | V | ISINK = 200 µA | 4 |
| Floating-State Leakage Current |  | -10 |  | 10 | µA |  | 4 |
| Normal Mode (Static) Supply Current | ITOTAL |  |  | 18 | mA | Digital inputs = 0 V or VDRIVE; AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V | 4 |
| Normal Mode (Operational) Supply Current | ITOTAL |  |  | 26 | mA | fSAMPLE = 250 kSPS, AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V | 4 |
| ISS (Operational) | ISS |  |  | 0.25 | mA | VSS = −16.5 V, fSAMPLE = 250 kSPS | 4 |
| IDD (Operational) | IDD |  |  | 0.25 | mA | VDD = 16.5 V, fSAMPLE = 250 kSPS | 4 |
| Partial Power-Down Mode Current |  |  |  | 7 | mA | AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V | 4 |
| Full Power-Down Mode Current (STBY pin) |  |  |  | 60 | µA | SCLK on or off, AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V | 4 |
| Full Power-Down Mode Power Dissipation (STBY pin) |  |  |  | 315 | µW | AVCC = DVCC = VDRIVE = 5.25 V, VDD = 16.5 V, VSS = −16.5 V | 4 |
| VDD Range | VDD | 6 |  | 16.5 | V | For the ±4 × VREF range, VDD = 11 V to 16.5 V | 4 |
| VSS Range | VSS | -16.5 |  | -6 | V | For the ±4 × VREF range, VSS = −11 V to −16.5 V | 4 |
| AVCC Supply Voltage | AVCC | 4.75 |  | 5.25 | V |  | 4 |
| DVCC Supply Voltage | DVCC | 4.75 |  | 5.25 | V |  | 4 |
| VDRIVE Supply Voltage | VDRIVE | 2.7 |  | 5.25 | V |  | 4 |
| Minimum VDD/VSS Supply Voltage for ±4 × VREF Input Range |  | 11 |  |  | V | Analog input range ±4 × VREF, reference voltage 2.5 V | 15 |
| VDD to AGND, DGND |  | 0 |  | 16.5 | V |  | 6 |
| VSS to AGND, DGND |  | -16.5 |  | 0 | V |  | 6 |
| AVCC to AGND, DGND |  | -0.3 |  | 7 | V |  | 6 |
| DVCC to DGND, AGND |  | -0.3 |  | 7 | V |  | 6 |
| AGND to DGND |  | -0.3 |  | 0.3 | V |  | 6 |
| Input Current to Any Pin Except Supplies |  | -10 |  | 10 | mA |  | 6 |
| Operating Temperature Range | TA | -40 |  | 85 | °C |  | 6 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 6 |
| Junction Temperature |  |  |  | 150 | °C |  | 6 |
| Conversion Time (internal clock) | tCONV |  | 3 |  | µs | Conversion time, internal clock | 5 |
| Minimum Quiet Time Between Bus Relinquish and Start of Next Conversion | tQUIET | 150 |  |  | ns |  | 5 |
| Acquisition Time | tACQ | 550 |  |  | ns |  | 5 |
| CONVST x High to BUSY High | t1 |  |  | 60 | ns |  | 5 |
| STBY Rising Edge to CONVST x Rising Edge (wake-up) | tWAKE-UP |  |  | 2 | ms | Not shown in figures | 5 |
| BUSY to RD Delay | t2 | 0 |  |  | ns |  | 5 |
| RD Pulse Width | t5 | 45 |  |  | ns | VDRIVE < 4.75 V | 5 |
| RD Pulse Width | t5 | 36 |  |  | ns | VDRIVE = 4.75 V to 5.25 V | 5 |
| Data Access Time after RD Falling Edge | t6 |  |  | 45 | ns | VDRIVE < 4.75 V | 5 |
| Data Access Time after RD Falling Edge | t6 |  |  | 36 | ns | VDRIVE = 4.75 V to 5.25 V | 5 |
| Bus Relinquish Time after RD Rising Edge | t8 |  |  | 12 | ns |  | 5 |
| WR Pulse Width | t11 | 15 |  |  | ns |  | 5 |
| Frequency of Serial Read Clock | fSCLK |  |  | 18 | MHz |  | 5 |
| Delay from CS until DOUT x Three-State Disabled | t16 |  |  | 12 | ns |  | 5 |
| Data Access Time after SCLK Rising Edge/CS Falling Edge | t17 |  |  | 22 | ns |  | 5 |
| CS Rising Edge to DOUT x High Impedance | t21 |  |  | 18 | ns |  | 5 |
| Thermal Resistance Junction-to-Ambient (64-Lead LQFP) | θJA |  | 45 |  | °C/W | Device soldered in 4-layer circuit board | 6 |
| Thermal Resistance Junction-to-Case (64-Lead LQFP) | θJC |  | 11 |  | °C/W |  | 6 |

## CAD (KiCad official)

- Symbol: `AD7656A-1BSTZ`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `ad7656a-1bstz-etched.step` / `ad7656a-1bstz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7656a-1bstz.step` / `ad7656a-1bstz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7656A-1.pdf) (28 pp, sha256 `1cf58573a1cb97c1`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad7656a-1bstz-datasheet.pdf)