AD7655ASTZRL

{
  "slug": "ad7655astzrl",
  "version": "0.1.0",
  "type": "component",
  "description": "Analog Devices Analog To Digital Converters (ADC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "data acquisition",
    "ad7655astzrl",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ad7655astzrl.kicad_sym",
    "ad7655astzrl.kicad_mod",
    "ad7655astzrl.glb",
    "ad7655astzrl.step",
    "ad7655astzrl.lbr",
    "docs/hero.png",
    "docs/ad7655astzrl-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ad7655astzrl-hero.glb",
    "ad7655astzrl-hero.overlay.json",
    "ad7655astzrl-etched.glb"
  ],
  "component": {
    "mpn": "AD7655ASTZRL",
    "manufacturer": "Analog Devices",
    "package": "LQFP-48(7x7)",
    "pin_count": 48,
    "category": "Data Acquisition",
    "subcategory": "Analog To Digital Converters (ADC)",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588883992209215488",
    "parts": {
      "symbol": "ad7655astzrl.kicad_sym",
      "footprint": "ad7655astzrl.kicad_mod",
      "model_3d": "ad7655astzrl-hero.glb",
      "model_3d_plain": "ad7655astzrl-etched.glb",
      "model_3d_step": "ad7655astzrl-etched.step",
      "model_3d_step_plain": "ad7655astzrl.step",
      "lbr": "ad7655astzrl.lbr"
    },
    "distributor_links": {
      "lcsc": "C403856",
      "digikey": "AD7655ASTZRLTR-ND",
      "mouser": "584-AD7655ASTZR"
    },
    "distributor_check": {
      "checked_at": "2026-10-18T01:37:57Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "AD7655ASTZRLTR-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "584-AD7655ASTZR",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog power ground pin, the ground to which most internal ADC analog signals are referenced and which must be connected with the least resistance to the analog ground plane."
      },
      {
        "number": "2",
        "name": "AVDD",
        "type": "power_in",
        "description": "Input analog power pin, nominally 5 V."
      },
      {
        "number": "3",
        "name": "A0",
        "type": "input",
        "description": "Multiplexer select: when LOW, INA1 and INB1 are sampled simultaneously then converted; when HIGH, INA2 and INB2 are sampled simultaneously then converted."
      },
      {
        "number": "4",
        "name": "BYTESWAP",
        "type": "input",
        "description": "Parallel mode 8/16-bit byte selection: when LOW the LSB is output on D[7:0] and the MSB on D[15:8]; when HIGH the LSB is output on D[15:8] and the MSB on D[7:0]."
      },
      {
        "number": "5",
        "name": "A/B",
        "type": "input",
        "description": "Data channel selection: in parallel mode LOW reads Channel B and HIGH reads Channel A; in serial mode HIGH outputs Channel A first, LOW outputs Channel B first."
      },
      {
        "number": "6",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital power ground pin."
      },
      {
        "number": "7",
        "name": "IMPULSE",
        "type": "input",
        "description": "Mode selection: when HIGH, selects a reduced power mode in which power dissipation is approximately proportional to the sampling rate."
      },
      {
        "number": "8",
        "name": "SER/PAR",
        "type": "input",
        "description": "Serial/parallel selection: when LOW the parallel port is selected; when HIGH the serial interface mode is selected and some DATA bus bits are used as a serial port."
      },
      {
        "number": "9",
        "name": "D0",
        "type": "output",
        "description": "Bit 0 of the parallel port data output bus; high impedance when SER/PAR is HIGH."
      },
      {
        "number": "10",
        "name": "D1",
        "type": "output",
        "description": "Bit 1 of the parallel port data output bus; high impedance when SER/PAR is HIGH."
      },
      {
        "number": "11",
        "name": "D2/DIVSCLK[0]",
        "type": "bidirectional",
        "description": "Bit 2 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW it is a serial input that slows the internal serial clock."
      },
      {
        "number": "12",
        "name": "D3/DIVSCLK[1]",
        "type": "bidirectional",
        "description": "Bit 3 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW it is a serial input that slows the internal serial clock."
      },
      {
        "number": "13",
        "name": "D4/EXT/INT",
        "type": "bidirectional",
        "description": "Bit 4 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it selects internal (LOW) or external (HIGH) data clock, master or slave mode."
      },
      {
        "number": "14",
        "name": "D5/INVSYNC",
        "type": "bidirectional",
        "description": "Bit 5 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it selects the active state of SYNC in master modes (LOW = active HIGH, HIGH = active LOW)."
      },
      {
        "number": "15",
        "name": "D6/INVSCLK",
        "type": "bidirectional",
        "description": "Bit 6 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it inverts the SCLK signal in both master and slave modes."
      },
      {
        "number": "16",
        "name": "D7/RDC/SDIN",
        "type": "bidirectional",
        "description": "Bit 7 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it is an external daisy-chain data input (EXT/INT HIGH) or the read-mode select (EXT/INT LOW)."
      },
      {
        "number": "17",
        "name": "OGND",
        "type": "power_in",
        "description": "Input/output interface digital power ground."
      },
      {
        "number": "18",
        "name": "OVDD",
        "type": "power_in",
        "description": "Input/output interface digital power, nominally at the same supply as the host interface (5 V or 3 V)."
      },
      {
        "number": "19",
        "name": "DVDD",
        "type": "power_in",
        "description": "Digital power, nominally 5 V."
      },
      {
        "number": "20",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital power ground pin."
      },
      {
        "number": "21",
        "name": "D8/SDOUT",
        "type": "output",
        "description": "Bit 8 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it is the serial data output, synchronized to SCLK."
      },
      {
        "number": "22",
        "name": "D9/SCLK",
        "type": "bidirectional",
        "description": "Bit 9 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it is the serial data clock input or output, depending on EXT/INT."
      },
      {
        "number": "23",
        "name": "D10/SYNC",
        "type": "output",
        "description": "Bit 10 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it is the digital frame synchronization output for the internal data clock (EXT/INT LOW)."
      },
      {
        "number": "24",
        "name": "D11/RDERROR",
        "type": "output",
        "description": "Bit 11 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH and EXT/INT is HIGH it is the incomplete read error flag, pulsed HIGH in slave mode."
      },
      {
        "number": "25",
        "name": "D12",
        "type": "output",
        "description": "Bit 12 of the parallel port data output bus; high impedance when SER/PAR is HIGH."
      },
      {
        "number": "26",
        "name": "D13",
        "type": "output",
        "description": "Bit 13 of the parallel port data output bus; high impedance when SER/PAR is HIGH."
      },
      {
        "number": "27",
        "name": "D14",
        "type": "output",
        "description": "Bit 14 of the parallel port data output bus; high impedance when SER/PAR is HIGH."
      },
      {
        "number": "28",
        "name": "D15",
        "type": "output",
        "description": "Bit 15 of the parallel port data output bus; high impedance when SER/PAR is HIGH."
      },
      {
        "number": "29",
        "name": "BUSY",
        "type": "output",
        "description": "Busy output: goes HIGH when a conversion starts and stays HIGH until both conversions are complete and the data is latched; its falling edge can be used as a data-ready clock."
      },
      {
        "number": "30",
        "name": "EOC",
        "type": "output",
        "description": "End of convert output: goes LOW at each channel conversion."
      },
      {
        "number": "31",
        "name": "RD",
        "type": "input",
        "description": "Read data: when CS and RD are both LOW, the parallel or serial output bus is enabled."
      },
      {
        "number": "32",
        "name": "CS",
        "type": "input",
        "description": "Chip select: when CS and RD are both LOW, the output bus is enabled; CS also gates the external serial clock."
      },
      {
        "number": "33",
        "name": "RESET",
        "type": "input",
        "description": "Reset input: when HIGH, resets the AD7655 and aborts any current conversion; tie to DGND if not used."
      },
      {
        "number": "34",
        "name": "PD",
        "type": "input",
        "description": "Power-down input: when HIGH, power consumption is reduced and conversions are inhibited after the current conversion completes."
      },
      {
        "number": "35",
        "name": "CNVST",
        "type": "input",
        "description": "Start conversion: a falling edge puts the sample-and-hold into hold and starts a conversion; in impulse mode, if held LOW when acquisition is complete, a conversion starts immediately."
      },
      {
        "number": "36",
        "name": "DVDD",
        "type": "power_in",
        "description": "Digital power, nominally 5 V."
      },
      {
        "number": "37",
        "name": "REF",
        "type": "passive",
        "description": "Reference input pin providing the reference to the converter; the external reference voltage range is 2.3 V to AVDD/2 V (Table 2)."
      },
      {
        "number": "38",
        "name": "REFGND",
        "type": "passive",
        "description": "Reference input analog ground; it carries pulsed currents and should be a low-impedance return to the reference."
      },
      {
        "number": "39",
        "name": "INB1",
        "type": "passive",
        "description": "Channel B analog input 1; the input voltage range VINx - VINxN is 0 V to 2 x VREF (Table 2)."
      },
      {
        "number": "40",
        "name": "INBN",
        "type": "passive",
        "description": "Channel B analog input ground sense, allowing the channel ground to be sensed independently; common-mode input range is -0.1 V to +0.5 V (Table 2)."
      },
      {
        "number": "41",
        "name": "INB2",
        "type": "passive",
        "description": "Channel B analog input 2; the input voltage range VINx - VINxN is 0 V to 2 x VREF (Table 2)."
      },
      {
        "number": "42",
        "name": "REFB",
        "type": "passive",
        "description": "Reference input applied to Channel B."
      },
      {
        "number": "43",
        "name": "REFA",
        "type": "passive",
        "description": "Reference input applied to Channel A."
      },
      {
        "number": "44",
        "name": "INA2",
        "type": "passive",
        "description": "Channel A analog input 2; the input voltage range VINx - VINxN is 0 V to 2 x VREF (Table 2)."
      },
      {
        "number": "45",
        "name": "INAN",
        "type": "passive",
        "description": "Channel A analog input ground sense, allowing the channel ground to be sensed independently; common-mode input range is -0.1 V to +0.5 V (Table 2)."
      },
      {
        "number": "46",
        "name": "INA1",
        "type": "passive",
        "description": "Channel A analog input 1; the input voltage range VINx - VINxN is 0 V to 2 x VREF (Table 2)."
      },
      {
        "number": "47",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog power ground pin."
      },
      {
        "number": "48",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog power ground pin."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Package hint conflict: the hint says LQFP-48 (7x7), but the datasheet gives the ST-48 LQFP body as 9; The exposed pad (EPAD) on the LFCSP/LQFP is not a numbered pin, so it is not listed. Per the datashe; Pin types for analog inputs and references (AI in the datasheet) have no direct KiCad ERC class; the"
        ],
        "pages_sent": 10,
        "cost_usd": 0.1007,
        "at": "2026-10-18T01:35:49"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588883992209215488",
        "pages": 26,
        "sha256": "7b36380447447657",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 48,
        "described": 48,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ad7655astzrl.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          9.0,
          9.0,
          1.5
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "9dea352d93177c2904afd7d7b68ea8855ce1ab691f69f8b3e13655600514b6bf",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ad7655astzrl-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          9.0,
          9.0,
          1.5
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "5d8fce3a9438c2fda93a8268a4223d22ed3fe42acf0b50d09aafdcaea59991f3",
        "checked": "2026-10-18",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}