AD7655ASTZRL

Analog Devices · Analog To Digital Converters (ADC) · LQFP-48(7x7)

AD7655ASTZRL from Analog Devices, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AGND	power_in	Analog power ground pin, the ground to which most internal ADC analog signals are referenced and which must be connected with the least resistance to the analog ground plane.
2	AVDD	power_in	Input analog power pin, nominally 5 V.
3	A0	input	Multiplexer select: when LOW, INA1 and INB1 are sampled simultaneously then converted; when HIGH, INA2 and INB2 are sampled simultaneously then converted.
4	BYTESWAP	input	Parallel mode 8/16-bit byte selection: when LOW the LSB is output on D[7:0] and the MSB on D[15:8]; when HIGH the LSB is output on D[15:8] and the MSB on D[7:0].
5	A/B	input	Data channel selection: in parallel mode LOW reads Channel B and HIGH reads Channel A; in serial mode HIGH outputs Channel A first, LOW outputs Channel B first.
6	DGND	power_in	Digital power ground pin.
7	IMPULSE	input	Mode selection: when HIGH, selects a reduced power mode in which power dissipation is approximately proportional to the sampling rate.
8	SER/PAR	input	Serial/parallel selection: when LOW the parallel port is selected; when HIGH the serial interface mode is selected and some DATA bus bits are used as a serial port.
9	D0	output	Bit 0 of the parallel port data output bus; high impedance when SER/PAR is HIGH.
10	D1	output	Bit 1 of the parallel port data output bus; high impedance when SER/PAR is HIGH.
11	D2/DIVSCLK[0]	bidirectional	Bit 2 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW it is a serial input that slows the internal serial clock.
12	D3/DIVSCLK[1]	bidirectional	Bit 3 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW it is a serial input that slows the internal serial clock.
13	D4/EXT/INT	bidirectional	Bit 4 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it selects internal (LOW) or external (HIGH) data clock, master or slave mode.
14	D5/INVSYNC	bidirectional	Bit 5 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it selects the active state of SYNC in master modes (LOW = active HIGH, HIGH = active LOW).
15	D6/INVSCLK	bidirectional	Bit 6 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it inverts the SCLK signal in both master and slave modes.
16	D7/RDC/SDIN	bidirectional	Bit 7 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it is an external daisy-chain data input (EXT/INT HIGH) or the read-mode select (EXT/INT LOW).
17	OGND	power_in	Input/output interface digital power ground.
18	OVDD	power_in	Input/output interface digital power, nominally at the same supply as the host interface (5 V or 3 V).
19	DVDD	power_in	Digital power, nominally 5 V.
20	DGND	power_in	Digital power ground pin.
21	D8/SDOUT	output	Bit 8 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it is the serial data output, synchronized to SCLK.
22	D9/SCLK	bidirectional	Bit 9 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it is the serial data clock input or output, depending on EXT/INT.
23	D10/SYNC	output	Bit 10 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it is the digital frame synchronization output for the internal data clock (EXT/INT LOW).
24	D11/RDERROR	output	Bit 11 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH and EXT/INT is HIGH it is the incomplete read error flag, pulsed HIGH in slave mode.
25	D12	output	Bit 12 of the parallel port data output bus; high impedance when SER/PAR is HIGH.
26	D13	output	Bit 13 of the parallel port data output bus; high impedance when SER/PAR is HIGH.
27	D14	output	Bit 14 of the parallel port data output bus; high impedance when SER/PAR is HIGH.
28	D15	output	Bit 15 of the parallel port data output bus; high impedance when SER/PAR is HIGH.
29	BUSY	output	Busy output: goes HIGH when a conversion starts and stays HIGH until both conversions are complete and the data is latched; its falling edge can be used as a data-ready clock.
30	EOC	output	End of convert output: goes LOW at each channel conversion.
31	RD	input	Read data: when CS and RD are both LOW, the parallel or serial output bus is enabled.
32	CS	input	Chip select: when CS and RD are both LOW, the output bus is enabled; CS also gates the external serial clock.
33	RESET	input	Reset input: when HIGH, resets the AD7655 and aborts any current conversion; tie to DGND if not used.
34	PD	input	Power-down input: when HIGH, power consumption is reduced and conversions are inhibited after the current conversion completes.
35	CNVST	input	Start conversion: a falling edge puts the sample-and-hold into hold and starts a conversion; in impulse mode, if held LOW when acquisition is complete, a conversion starts immediately.
36	DVDD	power_in	Digital power, nominally 5 V.
37	REF	passive	Reference input pin providing the reference to the converter; the external reference voltage range is 2.3 V to AVDD/2 V (Table 2).
38	REFGND	passive	Reference input analog ground; it carries pulsed currents and should be a low-impedance return to the reference.
39	INB1	passive	Channel B analog input 1; the input voltage range VINx - VINxN is 0 V to 2 x VREF (Table 2).
40	INBN	passive	Channel B analog input ground sense, allowing the channel ground to be sensed independently; common-mode input range is -0.1 V to +0.5 V (Table 2).
41	INB2	passive	Channel B analog input 2; the input voltage range VINx - VINxN is 0 V to 2 x VREF (Table 2).
42	REFB	passive	Reference input applied to Channel B.
43	REFA	passive	Reference input applied to Channel A.
44	INA2	passive	Channel A analog input 2; the input voltage range VINx - VINxN is 0 V to 2 x VREF (Table 2).
45	INAN	passive	Channel A analog input ground sense, allowing the channel ground to be sensed independently; common-mode input range is -0.1 V to +0.5 V (Table 2).
46	INA1	passive	Channel A analog input 1; the input voltage range VINx - VINxN is 0 V to 2 x VREF (Table 2).
47	AGND	power_in	Analog power ground pin.
48	AGND	power_in	Analog power ground pin.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LQFP-48(7x7)
Category	Data Acquisition
Pins	48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Voltage Range VINx, VINxN		0			V		3
Common-Mode Input Voltage VINxN		-0.1		0.5	V		3
Throughput Rate		0		500	kSPS	Normal mode	3
Throughput Rate		0		444	kSPS	Impulse mode	3
Integral Linearity Error		-6		6	LSB		3
No Missing Codes		15			Bits		3
Full-Scale Error		-0.5		0.5	% of FSR	TMIN to TMAX	3
Full-Scale Error Drift		-2		2	ppm/°C		3
Unipolar Zero Error		-0.25		0.25	% of FSR	TMIN to TMAX	3
Unipolar Zero Error Drift		-0.8		0.8	ppm/°C		3
Power Supply Sensitivity		-0.8		0.8	LSB	AVDD = 5 V ± 5%	3
Signal-to-Noise		86			dB	fIN = 100 kHz	3
Spurious-Free Dynamic Range		98			dB	fIN = 100 kHz	3
Total Harmonic Distortion				-96	dB	fIN = 100 kHz	3
Signal-to-Noise and Distortion		86			dB	fIN = 100 kHz	3
Signal-to-Noise and Distortion		30			dB	fIN = 100 kHz, −60 dB input	3
Channel-to-Channel Isolation				-92	dB	fIN = 100 kHz	3
Complete Cycle (2 Channels)				2	µs	Normal mode	3
Complete Cycle (2 Channels)				2.25	µs	Impulse mode	3
Transient Response				250	ns	Full-scale step	3
External Reference Voltage Range		2.3	2.5		V		3
Logic Input Low Voltage	VIL	-0.3		0.8	V		3
Logic Input High Voltage	VIH	2			V		3
Input Leakage Current Low	IIL	-1		1	µA		3
Input Leakage Current High	IIH	-1		1	µA		3
Digital Output Low Voltage	VOL			0.4	V	ISINK = 1.6 mA	3
External SCLK Setup Time	t38	5			ns	Slave serial interface mode	6
External SCLK Active Edge to SDOUT Delay	t39	3		18	ns	Slave serial interface mode	6
SDIN Setup Time	t40	5			ns	Slave serial interface mode	6
SDIN Hold Time	t41	5			ns	Slave serial interface mode	6
External SCLK Period	t42	25			ns	Slave serial interface mode	6
External SCLK High	t43	10			ns	Slave serial interface mode	6
External SCLK Low	t44	10			ns	Slave serial interface mode	6
Analog Input CMRR			55		dB	fIN = 100 kHz	3
Input Current			45		µA	500 kSPS throughput	3
External Reference Current Drain			180		µA	500 kSPS throughput	3
Transition Noise			0.8		LSB		3
−3 dB Input Bandwidth			10		MHz		3
Aperture Delay			2		ns		3
Aperture Delay Matching			30		ps		3
Aperture Jitter			5		ps rms		3
Ground Voltage Differences (AGND, DGND, OGND)		-0.3		0.3	V		7
Supply Voltages (AVDD, DVDD, OVDD)		-0.3		7	V		7
AVDD to DVDD, AVDD to OVDD		-7		7	V		7
DVDD to OVDD		-0.3		7	V		7
Digital Inputs		-0.3			V		7
Internal Power Dissipation				700	mW	Free air, 48-lead LQFP	7
Junction Temperature				150	°C		7
Storage Temperature Range		-65		150	°C		7
Lead Temperature Range				300	°C	Soldering 10 sec	7
Thermal Resistance, Junction-to-Ambient	θJA		91		°C/W	48-lead LQFP, free air	7
Thermal Resistance, Junction-to-Case	θJC		30		°C/W	48-lead LQFP	7
Supply Voltage OVDD	OVDD	2.7		5.25	V	AVDD = DVDD = 5 V	3
Operating Temperature Range		-40		85	°C		1

CAD (KiCad official)

Symbol: AD7655ASTZRL
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: ad7655astzrl-etched.step / ad7655astzrl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7655astzrl.step / ad7655astzrl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (26 pp, sha256 7b36380447447657, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# AD7655ASTZRL

**Analog Devices** · Analog To Digital Converters (ADC) · LQFP-48(7x7)

AD7655ASTZRL from Analog Devices, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AGND | power_in | Analog power ground pin, the ground to which most internal ADC analog signals are referenced and which must be connected with the least resistance to the analog ground plane. |
| 2 | AVDD | power_in | Input analog power pin, nominally 5 V. |
| 3 | A0 | input | Multiplexer select: when LOW, INA1 and INB1 are sampled simultaneously then converted; when HIGH, INA2 and INB2 are sampled simultaneously then converted. |
| 4 | BYTESWAP | input | Parallel mode 8/16-bit byte selection: when LOW the LSB is output on D[7:0] and the MSB on D[15:8]; when HIGH the LSB is output on D[15:8] and the MSB on D[7:0]. |
| 5 | A/B | input | Data channel selection: in parallel mode LOW reads Channel B and HIGH reads Channel A; in serial mode HIGH outputs Channel A first, LOW outputs Channel B first. |
| 6 | DGND | power_in | Digital power ground pin. |
| 7 | IMPULSE | input | Mode selection: when HIGH, selects a reduced power mode in which power dissipation is approximately proportional to the sampling rate. |
| 8 | SER/PAR | input | Serial/parallel selection: when LOW the parallel port is selected; when HIGH the serial interface mode is selected and some DATA bus bits are used as a serial port. |
| 9 | D0 | output | Bit 0 of the parallel port data output bus; high impedance when SER/PAR is HIGH. |
| 10 | D1 | output | Bit 1 of the parallel port data output bus; high impedance when SER/PAR is HIGH. |
| 11 | D2/DIVSCLK[0] | bidirectional | Bit 2 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW it is a serial input that slows the internal serial clock. |
| 12 | D3/DIVSCLK[1] | bidirectional | Bit 3 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW it is a serial input that slows the internal serial clock. |
| 13 | D4/EXT/INT | bidirectional | Bit 4 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it selects internal (LOW) or external (HIGH) data clock, master or slave mode. |
| 14 | D5/INVSYNC | bidirectional | Bit 5 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it selects the active state of SYNC in master modes (LOW = active HIGH, HIGH = active LOW). |
| 15 | D6/INVSCLK | bidirectional | Bit 6 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it inverts the SCLK signal in both master and slave modes. |
| 16 | D7/RDC/SDIN | bidirectional | Bit 7 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it is an external daisy-chain data input (EXT/INT HIGH) or the read-mode select (EXT/INT LOW). |
| 17 | OGND | power_in | Input/output interface digital power ground. |
| 18 | OVDD | power_in | Input/output interface digital power, nominally at the same supply as the host interface (5 V or 3 V). |
| 19 | DVDD | power_in | Digital power, nominally 5 V. |
| 20 | DGND | power_in | Digital power ground pin. |
| 21 | D8/SDOUT | output | Bit 8 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it is the serial data output, synchronized to SCLK. |
| 22 | D9/SCLK | bidirectional | Bit 9 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it is the serial data clock input or output, depending on EXT/INT. |
| 23 | D10/SYNC | output | Bit 10 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH it is the digital frame synchronization output for the internal data clock (EXT/INT LOW). |
| 24 | D11/RDERROR | output | Bit 11 of the parallel port data output bus when SER/PAR is LOW; when SER/PAR is HIGH and EXT/INT is HIGH it is the incomplete read error flag, pulsed HIGH in slave mode. |
| 25 | D12 | output | Bit 12 of the parallel port data output bus; high impedance when SER/PAR is HIGH. |
| 26 | D13 | output | Bit 13 of the parallel port data output bus; high impedance when SER/PAR is HIGH. |
| 27 | D14 | output | Bit 14 of the parallel port data output bus; high impedance when SER/PAR is HIGH. |
| 28 | D15 | output | Bit 15 of the parallel port data output bus; high impedance when SER/PAR is HIGH. |
| 29 | BUSY | output | Busy output: goes HIGH when a conversion starts and stays HIGH until both conversions are complete and the data is latched; its falling edge can be used as a data-ready clock. |
| 30 | EOC | output | End of convert output: goes LOW at each channel conversion. |
| 31 | RD | input | Read data: when CS and RD are both LOW, the parallel or serial output bus is enabled. |
| 32 | CS | input | Chip select: when CS and RD are both LOW, the output bus is enabled; CS also gates the external serial clock. |
| 33 | RESET | input | Reset input: when HIGH, resets the AD7655 and aborts any current conversion; tie to DGND if not used. |
| 34 | PD | input | Power-down input: when HIGH, power consumption is reduced and conversions are inhibited after the current conversion completes. |
| 35 | CNVST | input | Start conversion: a falling edge puts the sample-and-hold into hold and starts a conversion; in impulse mode, if held LOW when acquisition is complete, a conversion starts immediately. |
| 36 | DVDD | power_in | Digital power, nominally 5 V. |
| 37 | REF | passive | Reference input pin providing the reference to the converter; the external reference voltage range is 2.3 V to AVDD/2 V (Table 2). |
| 38 | REFGND | passive | Reference input analog ground; it carries pulsed currents and should be a low-impedance return to the reference. |
| 39 | INB1 | passive | Channel B analog input 1; the input voltage range VINx - VINxN is 0 V to 2 x VREF (Table 2). |
| 40 | INBN | passive | Channel B analog input ground sense, allowing the channel ground to be sensed independently; common-mode input range is -0.1 V to +0.5 V (Table 2). |
| 41 | INB2 | passive | Channel B analog input 2; the input voltage range VINx - VINxN is 0 V to 2 x VREF (Table 2). |
| 42 | REFB | passive | Reference input applied to Channel B. |
| 43 | REFA | passive | Reference input applied to Channel A. |
| 44 | INA2 | passive | Channel A analog input 2; the input voltage range VINx - VINxN is 0 V to 2 x VREF (Table 2). |
| 45 | INAN | passive | Channel A analog input ground sense, allowing the channel ground to be sensed independently; common-mode input range is -0.1 V to +0.5 V (Table 2). |
| 46 | INA1 | passive | Channel A analog input 1; the input voltage range VINx - VINxN is 0 V to 2 x VREF (Table 2). |
| 47 | AGND | power_in | Analog power ground pin. |
| 48 | AGND | power_in | Analog power ground pin. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LQFP-48(7x7) |
| Category | Data Acquisition |
| Pins | 48 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage Range VINx, VINxN |  | 0 |  |  | V |  | 3 |
| Common-Mode Input Voltage VINxN |  | -0.1 |  | 0.5 | V |  | 3 |
| Throughput Rate |  | 0 |  | 500 | kSPS | Normal mode | 3 |
| Throughput Rate |  | 0 |  | 444 | kSPS | Impulse mode | 3 |
| Integral Linearity Error |  | -6 |  | 6 | LSB |  | 3 |
| No Missing Codes |  | 15 |  |  | Bits |  | 3 |
| Full-Scale Error |  | -0.5 |  | 0.5 | % of FSR | TMIN to TMAX | 3 |
| Full-Scale Error Drift |  | -2 |  | 2 | ppm/°C |  | 3 |
| Unipolar Zero Error |  | -0.25 |  | 0.25 | % of FSR | TMIN to TMAX | 3 |
| Unipolar Zero Error Drift |  | -0.8 |  | 0.8 | ppm/°C |  | 3 |
| Power Supply Sensitivity |  | -0.8 |  | 0.8 | LSB | AVDD = 5 V ± 5% | 3 |
| Signal-to-Noise |  | 86 |  |  | dB | fIN = 100 kHz | 3 |
| Spurious-Free Dynamic Range |  | 98 |  |  | dB | fIN = 100 kHz | 3 |
| Total Harmonic Distortion |  |  |  | -96 | dB | fIN = 100 kHz | 3 |
| Signal-to-Noise and Distortion |  | 86 |  |  | dB | fIN = 100 kHz | 3 |
| Signal-to-Noise and Distortion |  | 30 |  |  | dB | fIN = 100 kHz, −60 dB input | 3 |
| Channel-to-Channel Isolation |  |  |  | -92 | dB | fIN = 100 kHz | 3 |
| Complete Cycle (2 Channels) |  |  |  | 2 | µs | Normal mode | 3 |
| Complete Cycle (2 Channels) |  |  |  | 2.25 | µs | Impulse mode | 3 |
| Transient Response |  |  |  | 250 | ns | Full-scale step | 3 |
| External Reference Voltage Range |  | 2.3 | 2.5 |  | V |  | 3 |
| Logic Input Low Voltage | VIL | -0.3 |  | 0.8 | V |  | 3 |
| Logic Input High Voltage | VIH | 2 |  |  | V |  | 3 |
| Input Leakage Current Low | IIL | -1 |  | 1 | µA |  | 3 |
| Input Leakage Current High | IIH | -1 |  | 1 | µA |  | 3 |
| Digital Output Low Voltage | VOL |  |  | 0.4 | V | ISINK = 1.6 mA | 3 |
| External SCLK Setup Time | t38 | 5 |  |  | ns | Slave serial interface mode | 6 |
| External SCLK Active Edge to SDOUT Delay | t39 | 3 |  | 18 | ns | Slave serial interface mode | 6 |
| SDIN Setup Time | t40 | 5 |  |  | ns | Slave serial interface mode | 6 |
| SDIN Hold Time | t41 | 5 |  |  | ns | Slave serial interface mode | 6 |
| External SCLK Period | t42 | 25 |  |  | ns | Slave serial interface mode | 6 |
| External SCLK High | t43 | 10 |  |  | ns | Slave serial interface mode | 6 |
| External SCLK Low | t44 | 10 |  |  | ns | Slave serial interface mode | 6 |
| Analog Input CMRR |  |  | 55 |  | dB | fIN = 100 kHz | 3 |
| Input Current |  |  | 45 |  | µA | 500 kSPS throughput | 3 |
| External Reference Current Drain |  |  | 180 |  | µA | 500 kSPS throughput | 3 |
| Transition Noise |  |  | 0.8 |  | LSB |  | 3 |
| −3 dB Input Bandwidth |  |  | 10 |  | MHz |  | 3 |
| Aperture Delay |  |  | 2 |  | ns |  | 3 |
| Aperture Delay Matching |  |  | 30 |  | ps |  | 3 |
| Aperture Jitter |  |  | 5 |  | ps rms |  | 3 |
| Ground Voltage Differences (AGND, DGND, OGND) |  | -0.3 |  | 0.3 | V |  | 7 |
| Supply Voltages (AVDD, DVDD, OVDD) |  | -0.3 |  | 7 | V |  | 7 |
| AVDD to DVDD, AVDD to OVDD |  | -7 |  | 7 | V |  | 7 |
| DVDD to OVDD |  | -0.3 |  | 7 | V |  | 7 |
| Digital Inputs |  | -0.3 |  |  | V |  | 7 |
| Internal Power Dissipation |  |  |  | 700 | mW | Free air, 48-lead LQFP | 7 |
| Junction Temperature |  |  |  | 150 | °C |  | 7 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 7 |
| Lead Temperature Range |  |  |  | 300 | °C | Soldering 10 sec | 7 |
| Thermal Resistance, Junction-to-Ambient | θJA |  | 91 |  | °C/W | 48-lead LQFP, free air | 7 |
| Thermal Resistance, Junction-to-Case | θJC |  | 30 |  | °C/W | 48-lead LQFP | 7 |
| Supply Voltage OVDD | OVDD | 2.7 |  | 5.25 | V | AVDD = DVDD = 5 V | 3 |
| Operating Temperature Range |  | -40 |  | 85 | °C |  | 1 |

## CAD (KiCad official)

- Symbol: `AD7655ASTZRL`
- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`
- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `ad7655astzrl-etched.step` / `ad7655astzrl-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7655astzrl.step` / `ad7655astzrl.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588883992209215488) (26 pp, sha256 `7b36380447447657`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad7655astzrl-datasheet.pdf)