# AD7610BCPZ

**Analog Devices** · Analog To Digital Converters (ADCs) · LFCSP-48(7x7)

AD7610BCPZ from Analog Devices, in a LFCSP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AGND | power_in | Analog power ground, the ground reference for all analog I/O, to be connected to the analog ground plane with AGND, DGND and OGND at the same potential. |
| 2 | AVDD | power_in | Analog power supply, nominally 4.75 V to 5.25 V, to be decoupled with 10 μF and 100 nF capacitors. |
| 3 | AGND | power_in | Analog power ground, the ground reference for all analog I/O, to be connected to the analog ground plane with AGND, DGND and OGND at the same potential. |
| 4 | BYTESWAP | input | Parallel mode byte selection: when high the LSB is output on D[15:8] and the MSB on D[7:0]; when low the reverse. |
| 5 | OB/2C | input | Output coding select: when high the output is straight binary, when low the MSB is inverted for twos complement output. |
| 6 | OGND | power_in | Interface digital power ground, the ground reference for digital outputs, ideally at the same potential as AGND and DGND. |
| 7 | OGND | power_in | Interface digital power ground, the ground reference for digital outputs, ideally at the same potential as AGND and DGND. |
| 8 | SER/PAR | input | Serial/parallel selection: low selects parallel mode, high selects the serial modes. |
| 9 | D0 | output | Bit 0 of the parallel port data output bus, always an output regardless of the SER/PAR state. |
| 10 | D1 | output | Bit 1 of the parallel port data output bus, always an output regardless of the SER/PAR state. |
| 11 | D2/DIVSCLK[0] | bidirectional | In parallel mode Bit 2 of the data output bus; in serial master read-after-convert mode DIVSCLK[0] slows the internal serial data clock. |
| 12 | D3/DIVSCLK[1] | bidirectional | In parallel mode Bit 3 of the data output bus; in serial master read-after-convert mode DIVSCLK[1] slows the internal serial data clock. |
| 13 | D4/EXT/INT | bidirectional | In parallel mode Bit 4 of the data output bus; in serial mode EXT/INT selects internal master clock (low) or external slave clock (high). |
| 14 | D5/INVSYNC | bidirectional | In parallel mode Bit 5 of the data output bus; in serial master mode INVSYNC selects the active level of SYNC. |
| 15 | D6/INVSCLK | bidirectional | In parallel mode Bit 6 of the data output bus; in serial modes INVSCLK selects the rising (low) or falling (high) edge of SDCLK/SCCLK. |
| 16 | D7/RDC/SDIN | bidirectional | In parallel mode Bit 7 of the data output bus; in serial mode it selects read-during-convert (RDC) or serves as serial data input SDIN for daisy-chaining. |
| 17 | OGND | power_in | Interface digital power ground, the ground reference for digital outputs, ideally at the same potential as AGND and DGND. |
| 18 | OVDD | power_in | Interface digital power, nominally 2.5 V, 3 V or 5 V matching the host interface, decoupled with 10 μF and 100 nF capacitors. |
| 19 | DVDD | power_in | Digital power, nominally 4.75 V to 5.25 V, decoupled with 10 μF and 100 nF capacitors; can be supplied from AVDD. |
| 20 | DGND | power_in | Digital power ground, the ground reference for digital circuitry, ideally at the same potential as AGND and OGND. |
| 21 | D8/SDOUT | output | In parallel mode Bit 8 of the data output bus; in serial modes SDOUT is the serial data output synchronized to SDCLK. |
| 22 | D9/SDCLK | bidirectional | In parallel mode Bit 9 of the data output bus; in serial modes SDCLK is the serial data clock input or output depending on EXT/INT. |
| 23 | D10/SYNC | output | In parallel mode Bit 10 of the data output bus; in serial master mode SYNC is the digital frame synchronization output. |
| 24 | D11/RDERROR | output | In parallel mode Bit 11 of the data output bus; in serial slave mode RDERROR is pulsed high when an incomplete data read is lost. |
| 25 | D12/HW/SW | bidirectional | In parallel mode Bit 12 of the data output bus; in serial mode HW/SW selects software (low) or hardware (high) configuration. |
| 26 | D13/SCIN | bidirectional | In parallel mode Bit 13 of the data output bus; in serial software configuration mode SCIN serially writes the configuration register MSB first. |
| 27 | D14/SCCLK | bidirectional | In parallel mode Bit 14 of the data output bus; in serial software configuration mode SCCLK clocks in the data on SCIN. |
| 28 | D15/SCCS | bidirectional | In parallel mode Bit 15 of the data output bus; in serial software configuration mode SCCS enables the serial configuration port. |
| 29 | BUSY | output | Busy output that goes high when a conversion starts and stays high until the conversion is complete and data is latched; its falling edge can serve as a data-ready clock. |
| 30 | TEN | input | Input range select used with BIPOLAR to set 0 V to 5 V, 0 V to 10 V, ±5 V or ±10 V ranges. |
| 31 | RD | input | Read data: when CS and RD are both low the parallel or serial output bus is enabled. |
| 32 | CS | input | Chip select: when CS and RD are both low the output bus is enabled; CS also gates the external clock in slave serial mode. |
| 33 | RESET | input | Reset input: when high it resets the AD7610 and aborts any conversion; the falling edge clears the configuration register. If unused, tie to OGND. |
| 34 | PD | input | Power-down input: when high the ADC is powered down, conversions are inhibited after the current one completes, and the digital interface remains active. |
| 35 | CNVST | input | Conversion start: a falling edge puts the sample-and-hold into hold and initiates a conversion. |
| 36 | BIPOLAR | input | Input range select used with TEN to choose the analog input range (see pin 30). |
| 37 | REF | passive | Reference input/output that produces 5 V when the internal reference is enabled, or accepts an external reference up to AVDD when disabled; requires at least 22 μF decoupling. |
| 38 | REFGND | passive | Reference input analog ground, connected to the analog ground plane and carrying pulsed reference currents, so it needs a low-impedance return. |
| 39 | IN− | passive | Analog input ground sense, connected to the analog ground plane or a remote sense ground. |
| 40 | VCC | power_in | High-voltage positive supply, normally +7 V to +15 V. |
| 41 | VEE | power_in | High-voltage negative supply, normally 0 V to −15 V (0 V in unipolar ranges). |
| 42 | AGND | power_in | Analog power ground, the ground reference for all analog I/O, to be connected to the analog ground plane with AGND, DGND and OGND at the same potential. |
| 43 | IN+ | input | Analog input referenced to IN−, sampled on the falling edge of CNVST. |
| 44 | AVDD | power_in | Analog power supply, nominally 4.75 V to 5.25 V, to be decoupled with 10 μF and 100 nF capacitors. |
| 45 | TEMP | output | Temperature sensor analog output, enabled when the internal reference is on (PDREF = PDBUF = low). |
| 46 | REFBUFIN | input | Reference buffer input: with an external reference and the internal buffer enabled, applying 2.5 V produces 5 V on REF. |
| 47 | PDREF | input | Internal reference power-down input: low enables the internal reference, high powers it down so an external reference must be used. |
| 48 | PDBUF | input | Internal reference buffer power-down input: low enables the buffer (required with the internal reference), high powers it down. |
| 49 | EPAD | passive | Exposed pad, not connected internally and recommended to be soldered to VEE on the LFCSP package. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-48(7x7) |
| Category | ADC/DAC/Data Conversion |
| Pins | 49 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Voltage Range VIN, 0 V to 5 V | VIN | -0.1 |  | 5.1 | V | VIN+ − VIN− = 0 V to 5 V | 3 |
| Voltage Range VIN, 0 V to 10 V | VIN | -0.1 |  | 10.1 | V | VIN+ − VIN− = 0 V to 10 V | 3 |
| Voltage Range VIN, ±5 V | VIN | -5.1 |  | 5.1 | V | VIN+ − VIN− = ±5 V | 3 |
| Voltage Range VIN, ±10 V | VIN | -10.1 |  | 10.1 | V | VIN+ − VIN− = ±10 V | 3 |
| Voltage Range VIN− to AGND | VIN− | -0.1 |  | 0.1 | V | VIN− to AGND | 3 |
| Analog Input CMRR |  | 75 |  |  | dB | fIN = 100 kHz | 3 |
| Integral Linearity Error | INL | -1.5 | 0.75 | 1.5 | LSB |  | 3 |
| Differential Linearity Error | DNL | -1 |  | 1.5 | LSB |  | 3 |
| Zero Error (Unipolar or Bipolar) |  | -35 |  | 35 | LSB | Unipolar or Bipolar | 3 |
| Zero Error Temperature Drift |  | -1 |  | 1 | ppm/°C |  | 3 |
| Bipolar Full-Scale Error |  | -50 |  | 50 | LSB |  | 3 |
| Unipolar Full-Scale Error |  | -70 |  | 70 | LSB |  | 3 |
| Full-Scale Error Temperature Drift |  | -1 |  | 1 | ppm/°C |  | 3 |
| Power Supply Sensitivity |  |  |  | 3 | LSB | AVDD = 5 V ± 5% | 3 |
| Throughput Rate |  |  |  | 250 | kSPS |  | 3 |
| Complete Cycle |  |  |  | 4 | μs |  | 3 |
| Dynamic Range |  | 92.5 | 93.5 |  | dB | VIN = 0 V to 5 V, fIN = 2 kHz, −60 dB | 3 |
| Signal-to-Noise Ratio | SNR | 92 | 93 |  | dB | VIN = 0 V to 5 V, 0 V to 10 V, fIN = 2 kHz | 3 |
| Internal Reference Output Voltage | REF | 4.965 | 5 | 5.035 | V | REF @ 25°C, PDREF = PDBUF = low | 3 |
| Internal Reference Temperature Drift |  | -3 |  | 3 | ppm/°C | −40°C to +85°C | 3 |
| Reference Line Regulation |  | -15 |  | 15 | ppm/V | AVDD = 5 V ± 5% | 3 |
| REFBUFIN Input Voltage Range | REFBUFIN | 2.4 | 2.5 | 2.6 | V | PDREF = high, PDBUF = low | 3 |
| Internal SDCLK Period | t19 | 30 |  | 45 | ns | DIVSCLK[1:0] = 00, master read after convert | 6 |
| SYNC to SDCLK First Edge Delay | t18 | 3 |  |  | ns | DIVSCLK[1:0] = 00, minimum | 6 |
| Internal SDCLK High | t20 | 15 |  |  | ns | DIVSCLK[1:0] = 00, minimum | 6 |
| Internal SDCLK Low | t21 | 10 |  |  | ns | DIVSCLK[1:0] = 00, minimum | 6 |
| SDOUT Valid Setup Time | t22 | 4 |  |  | ns | DIVSCLK[1:0] = 00, minimum | 6 |
| BUSY High Width | t28 |  |  | 2.25 | μs | DIVSCLK[1:0] = 00, maximum | 6 |
| Supply Voltages AVDD, DVDD, OVDD | AVDD, DVDD, OVDD | -0.3 |  | 7 | V |  | 7 |
| AVDD to DVDD, AVDD to OVDD |  | -7 |  | 7 | V |  | 7 |
| DVDD to OVDD |  | -7 |  | 7 | V |  | 7 |
| VCC to AGND, DGND | VCC | -0.3 |  | 16.5 | V |  | 7 |
| VEE to GND | VEE | -16.5 |  | 0.3 | V |  | 7 |
| Ground Voltage Differences AGND, DGND, OGND |  | -0.3 |  | 0.3 | V |  | 7 |
| PDREF, PDBUF Current |  | -20 |  | 20 | mA |  | 7 |
| Internal Power Dissipation |  |  |  | 2.5 | W | Free air, 48-Lead LFCSP | 7 |
| Junction Temperature |  |  |  | 125 | °C |  | 7 |
| Storage Temperature Range |  | -65 |  | 125 | °C |  | 7 |
| Thermal Resistance θJA | θJA |  | 26 |  | °C/W | Free air, 48-Lead LFCSP | 7 |
| Operating Temperature Range |  | -40 |  | 85 | °C | Operation is specified from −40°C to +85°C | 1 |
| AVDD Supply Voltage | AVDD | 4.75 |  | 5.25 | V | Nominal, decoupled with 10 μF and 100 nF | 8 |
| OVDD Supply Voltage | OVDD | 2.7 |  | 5.5 | V | Specification conditions | 3 |
| VCC Supply Voltage | VCC | 7 |  | 15 | V | Normally +7 V to +15 V | 10 |
| VEE Supply Voltage | VEE | -15 |  | 0 | V | Normally 0 V to −15 V (0 V in unipolar ranges) | 10 |

## CAD (KiCad official)

- Symbol: `AD7610BCPZ`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: LFCSP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `ad7610bcpz-etched.step` / `ad7610bcpz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7610bcpz.step` / `ad7610bcpz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7610.pdf) (32 pp, sha256 `a489071c9d854fb9`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad7610bcpz-datasheet.pdf)