AD7609BSTZ

{
  "slug": "ad7609bstz",
  "version": "0.1.0",
  "type": "component",
  "description": "Analog Devices ADCs/DACs - Special Purpose, LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "data acquisition",
    "ad7609bstz",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
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    "README.md",
    "ad7609bstz.kicad_sym",
    "ad7609bstz.kicad_mod",
    "ad7609bstz.glb",
    "ad7609bstz.step",
    "ad7609bstz.lbr",
    "docs/hero.png",
    "docs/ad7609bstz-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ad7609bstz-hero.glb",
    "ad7609bstz-hero.overlay.json",
    "ad7609bstz-etched.glb"
  ],
  "component": {
    "mpn": "AD7609BSTZ",
    "manufacturer": "Analog Devices",
    "package": "LQFP-64(10x10)",
    "pin_count": 64,
    "category": "Data Acquisition",
    "subcategory": "ADCs/DACs - Special Purpose",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8758079679012458496",
    "parts": {
      "symbol": "ad7609bstz.kicad_sym",
      "footprint": "ad7609bstz.kicad_mod",
      "model_3d": "ad7609bstz-hero.glb",
      "model_3d_plain": "ad7609bstz-etched.glb",
      "model_3d_step": "ad7609bstz-etched.step",
      "model_3d_step_plain": "ad7609bstz.step",
      "lbr": "ad7609bstz.lbr"
    },
    "distributor_links": {
      "lcsc": "C514239",
      "digikey": "505-AD7609BSTZ-ND",
      "mouser": "584-AD7609BSTZ"
    },
    "distributor_check": {
      "checked_at": "2026-10-21T00:23:18Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "505-AD7609BSTZ-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "584-AD7609BSTZ",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "AVCC",
        "type": "power_in",
        "description": "Analog supply voltage of 4.75 V to 5.25 V feeds the front-end amplifiers and ADC core and should be decoupled to AGND."
      },
      {
        "number": "2",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog ground is the reference point for all analog circuitry and all six AGND pins should connect to the system AGND plane."
      },
      {
        "number": "3",
        "name": "OS 0",
        "type": "input",
        "description": "Oversampling mode control bit OS 0 (LSB) selects the oversampling ratio as decoded in Table 9."
      },
      {
        "number": "4",
        "name": "OS 1",
        "type": "input",
        "description": "Oversampling mode control bit OS 1 selects the oversampling ratio as decoded in Table 9."
      },
      {
        "number": "5",
        "name": "OS 2",
        "type": "input",
        "description": "Oversampling mode control bit OS 2 (MSB) selects the oversampling ratio as decoded in Table 9."
      },
      {
        "number": "6",
        "name": "PAR/SER SEL",
        "type": "input",
        "description": "A logic low selects the parallel interface and a logic high selects the serial interface."
      },
      {
        "number": "7",
        "name": "STBY",
        "type": "input",
        "description": "Places the device into standby or shutdown mode depending on the RANGE pin state (Table 8), with standby keeping the reference, regulators and regulator buffers powered."
      },
      {
        "number": "8",
        "name": "RANGE",
        "type": "input",
        "description": "A logic high sets the analog input range to ±20 V and a logic low sets it to ±10 V for all channels, and changing it during a conversion is not recommended."
      },
      {
        "number": "9",
        "name": "CONVST A",
        "type": "input",
        "description": "A rising edge puts the track-and-hold for V1 to V4 (or all channels if tied to CONVST B) into hold to start conversions, and it is only usable separately when oversampling is off."
      },
      {
        "number": "10",
        "name": "CONVST B",
        "type": "input",
        "description": "A rising edge puts the track-and-hold for V5 to V8 into hold when CONVST A and CONVST B are used separately, and it is only usable separately when oversampling is off."
      },
      {
        "number": "11",
        "name": "RESET",
        "type": "input",
        "description": "A rising edge of a high pulse (typically 100 ns wide) resets the device, must be applied after power-up, and aborts a conversion or zeros the output registers if applied during a conversion or read."
      },
      {
        "number": "12",
        "name": "RD/SCLK",
        "type": "input",
        "description": "Acts as the active-low parallel read control RD with CS in parallel mode, and as the serial clock input SCLK in serial mode."
      },
      {
        "number": "13",
        "name": "CS",
        "type": "input",
        "description": "Active-low chip select frames the data transfer, and with RD low enables the parallel output bus or frames the serial read."
      },
      {
        "number": "14",
        "name": "BUSY",
        "type": "output",
        "description": "Goes high after the CONVST A and CONVST B rising edges and falls when conversion data is latched into the output registers, so reads must finish before the BUSY falling edge."
      },
      {
        "number": "15",
        "name": "FRSTDATA",
        "type": "output",
        "description": "Indicates when the V1 result is being read on the parallel or serial interface, and is three-state while CS is high."
      },
      {
        "number": "16",
        "name": "DB0",
        "type": "tri_state",
        "description": "Parallel three-state data bit 0 outputs conversion bit DB2 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode."
      },
      {
        "number": "17",
        "name": "DB1",
        "type": "tri_state",
        "description": "Parallel three-state data bit 1 outputs conversion bit DB3 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode."
      },
      {
        "number": "18",
        "name": "DB2",
        "type": "tri_state",
        "description": "Parallel three-state data bit 2 outputs conversion bit DB4 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode."
      },
      {
        "number": "19",
        "name": "DB3",
        "type": "tri_state",
        "description": "Parallel three-state data bit 3 outputs conversion bit DB5 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode."
      },
      {
        "number": "20",
        "name": "DB4",
        "type": "tri_state",
        "description": "Parallel three-state data bit 4 outputs conversion bit DB6 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode."
      },
      {
        "number": "21",
        "name": "DB5",
        "type": "tri_state",
        "description": "Parallel three-state data bit 5 outputs conversion bit DB7 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode."
      },
      {
        "number": "22",
        "name": "DB6",
        "type": "tri_state",
        "description": "Parallel three-state data bit 6 outputs conversion bit DB8 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode."
      },
      {
        "number": "23",
        "name": "VDRIVE",
        "type": "power_in",
        "description": "Logic supply of 2.3 V to 5 V sets the interface operating voltage and is nominally the host interface supply."
      },
      {
        "number": "24",
        "name": "DB7/DOUTA",
        "type": "tri_state",
        "description": "Parallel data bit 7 outputs conversion bit DB9 when CS and RD are low, and functions as serial data output DOUTA when PAR/SER SEL is high."
      },
      {
        "number": "25",
        "name": "DB8/DOUTB",
        "type": "tri_state",
        "description": "Parallel data bit 8 outputs conversion bit DB10 when CS and RD are low, and functions as serial data output DOUTB when PAR/SER SEL is high."
      },
      {
        "number": "26",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog ground is the reference point for all analog circuitry and should connect to the system AGND plane."
      },
      {
        "number": "27",
        "name": "DB9",
        "type": "tri_state",
        "description": "Parallel three-state data bit 9 outputs conversion bit DB11 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode."
      },
      {
        "number": "28",
        "name": "DB10",
        "type": "tri_state",
        "description": "Parallel three-state data bit 10 outputs conversion bit DB12 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode."
      },
      {
        "number": "29",
        "name": "DB11",
        "type": "tri_state",
        "description": "Parallel three-state data bit 11 outputs conversion bit DB13 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode."
      },
      {
        "number": "30",
        "name": "DB12",
        "type": "tri_state",
        "description": "Parallel three-state data bit 12 outputs conversion bit DB14 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode."
      },
      {
        "number": "31",
        "name": "DB13",
        "type": "tri_state",
        "description": "Parallel three-state data bit 13 outputs conversion bit DB15 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode."
      },
      {
        "number": "32",
        "name": "DB14",
        "type": "tri_state",
        "description": "Parallel three-state data bit 14 outputs conversion bit DB16 on the first RD pulse and DB0 on the second, and is tied to AGND in serial mode."
      },
      {
        "number": "33",
        "name": "DB15",
        "type": "tri_state",
        "description": "Parallel three-state data bit 15 outputs conversion bit DB17 on the first RD pulse and DB1 on the second, and is tied to AGND in serial mode."
      },
      {
        "number": "34",
        "name": "REF SELECT",
        "type": "input",
        "description": "A logic high selects and enables the internal 2.5 V reference, while a logic low disables it and requires an external 2.5 V reference on REFIN/REFOUT."
      },
      {
        "number": "35",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog ground is the reference point for all analog circuitry and should connect to the system AGND plane."
      },
      {
        "number": "36",
        "name": "REGCAP",
        "type": "passive",
        "description": "Decoupling pin for the internal regulator output, which should be decoupled to AGND with a 1 µF capacitor and sits at 2.5 V to 2.7 V."
      },
      {
        "number": "37",
        "name": "AVCC",
        "type": "power_in",
        "description": "Analog supply voltage of 4.75 V to 5.25 V feeds the front-end amplifiers and ADC core and should be decoupled to AGND."
      },
      {
        "number": "38",
        "name": "AVCC",
        "type": "power_in",
        "description": "Analog supply voltage of 4.75 V to 5.25 V feeds the front-end amplifiers and ADC core and should be decoupled to AGND."
      },
      {
        "number": "39",
        "name": "REGCAP",
        "type": "passive",
        "description": "Decoupling pin for the internal regulator output, which should be decoupled to AGND with a 1 µF capacitor and sits at 2.5 V to 2.7 V."
      },
      {
        "number": "40",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog ground is the reference point for all analog circuitry and should connect to the system AGND plane."
      },
      {
        "number": "41",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog ground is the reference point for all analog circuitry and should connect to the system AGND plane."
      },
      {
        "number": "42",
        "name": "REFIN/REFOUT",
        "type": "bidirectional",
        "description": "Outputs the 2.5 V internal reference when REF SELECT is high or takes an external 2.5 V reference when it is low, and needs a 10 µF decoupling capacitor close to the REFGND pins."
      },
      {
        "number": "43",
        "name": "REFGND",
        "type": "power_in",
        "description": "Reference ground pin that should be connected to AGND."
      },
      {
        "number": "44",
        "name": "REFCAPA",
        "type": "passive",
        "description": "Reference buffer force/sense pin that must be tied to REFCAPB and decoupled to AGND with a low ESR 10 µF ceramic capacitor."
      },
      {
        "number": "45",
        "name": "REFCAPB",
        "type": "passive",
        "description": "Reference buffer force/sense pin that must be tied to REFCAPA and decoupled to AGND with a low ESR 10 µF ceramic capacitor."
      },
      {
        "number": "46",
        "name": "REFGND",
        "type": "power_in",
        "description": "Reference ground pin that should be connected to AGND."
      },
      {
        "number": "47",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog ground is the reference point for all analog circuitry and should connect to the system AGND plane."
      },
      {
        "number": "48",
        "name": "AVCC",
        "type": "power_in",
        "description": "Analog supply voltage of 4.75 V to 5.25 V feeds the front-end amplifiers and ADC core and should be decoupled to AGND."
      },
      {
        "number": "49",
        "name": "V1+",
        "type": "passive",
        "description": "Positive terminal of true differential analog input V1, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND."
      },
      {
        "number": "50",
        "name": "V1-",
        "type": "passive",
        "description": "Negative terminal of true differential analog input V1, which should be 180° out of phase with V1+ and is limited to ±16.5 V to AGND."
      },
      {
        "number": "51",
        "name": "V2+",
        "type": "passive",
        "description": "Positive terminal of true differential analog input V2, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND."
      },
      {
        "number": "52",
        "name": "V2-",
        "type": "passive",
        "description": "Negative terminal of true differential analog input V2, which should be 180° out of phase with V2+ and is limited to ±16.5 V to AGND."
      },
      {
        "number": "53",
        "name": "V3+",
        "type": "passive",
        "description": "Positive terminal of true differential analog input V3, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND."
      },
      {
        "number": "54",
        "name": "V3-",
        "type": "passive",
        "description": "Negative terminal of true differential analog input V3, which should be 180° out of phase with V3+ and is limited to ±16.5 V to AGND."
      },
      {
        "number": "55",
        "name": "V4+",
        "type": "passive",
        "description": "Positive terminal of true differential analog input V4, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND."
      },
      {
        "number": "56",
        "name": "V4-",
        "type": "passive",
        "description": "Negative terminal of true differential analog input V4, which should be 180° out of phase with V4+ and is limited to ±16.5 V to AGND."
      },
      {
        "number": "57",
        "name": "V5+",
        "type": "passive",
        "description": "Positive terminal of true differential analog input V5, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND."
      },
      {
        "number": "58",
        "name": "V5-",
        "type": "passive",
        "description": "Negative terminal of true differential analog input V5, which should be 180° out of phase with V5+ and is limited to ±16.5 V to AGND."
      },
      {
        "number": "59",
        "name": "V6+",
        "type": "passive",
        "description": "Positive terminal of true differential analog input V6, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND."
      },
      {
        "number": "60",
        "name": "V6-",
        "type": "passive",
        "description": "Negative terminal of true differential analog input V6, which should be 180° out of phase with V6+ and is limited to ±16.5 V to AGND."
      },
      {
        "number": "61",
        "name": "V7+",
        "type": "passive",
        "description": "Positive terminal of true differential analog input V7, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND."
      },
      {
        "number": "62",
        "name": "V7-",
        "type": "passive",
        "description": "Negative terminal of true differential analog input V7, which should be 180° out of phase with V7+ and is limited to ±16.5 V to AGND."
      },
      {
        "number": "63",
        "name": "V8+",
        "type": "passive",
        "description": "Positive terminal of true differential analog input V8, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND."
      },
      {
        "number": "64",
        "name": "V8-",
        "type": "passive",
        "description": "Negative terminal of true differential analog input V8, which should be 180° out of phase with V8+ and is limited to ±16.5 V to AGND."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The pin-configuration figure (Figure 7) is garbled in the text extraction, so the pin-number-to-name; Table 6 gives VDRIVE as 2.3 V to 5 V, while the Features list and the device description give 2.3 V ; KiCad ERC types are my classification from the datasheet's pin-type codes (P, AI, REF, DI, DO, DO/DI"
        ],
        "pages_sent": 11,
        "cost_usd": 0.1077,
        "at": "2026-10-21T00:19:16"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8758079679012458496",
        "pages": 36,
        "sha256": "8854f1daf3de5348",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 64,
        "described": 64,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
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        "sha256": "b0c827bc5c05552175d28affe44a5bd2ab45c9c36efff6ff07a74cc449b13db4",
        "checked": "2026-10-21",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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        "sha256": "5a2bffcd506421b8e9f4858e4871a2b95cb7b677b2108d4695010f23bc2d5054",
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}