AD7609BSTZ

Analog Devices · ADCs/DACs - Special Purpose · LQFP-64(10x10)

AD7609BSTZ from Analog Devices, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AVCC	power_in	Analog supply voltage of 4.75 V to 5.25 V feeds the front-end amplifiers and ADC core and should be decoupled to AGND.
2	AGND	power_in	Analog ground is the reference point for all analog circuitry and all six AGND pins should connect to the system AGND plane.
3	OS 0	input	Oversampling mode control bit OS 0 (LSB) selects the oversampling ratio as decoded in Table 9.
4	OS 1	input	Oversampling mode control bit OS 1 selects the oversampling ratio as decoded in Table 9.
5	OS 2	input	Oversampling mode control bit OS 2 (MSB) selects the oversampling ratio as decoded in Table 9.
6	PAR/SER SEL	input	A logic low selects the parallel interface and a logic high selects the serial interface.
7	STBY	input	Places the device into standby or shutdown mode depending on the RANGE pin state (Table 8), with standby keeping the reference, regulators and regulator buffers powered.
8	RANGE	input	A logic high sets the analog input range to ±20 V and a logic low sets it to ±10 V for all channels, and changing it during a conversion is not recommended.
9	CONVST A	input	A rising edge puts the track-and-hold for V1 to V4 (or all channels if tied to CONVST B) into hold to start conversions, and it is only usable separately when oversampling is off.
10	CONVST B	input	A rising edge puts the track-and-hold for V5 to V8 into hold when CONVST A and CONVST B are used separately, and it is only usable separately when oversampling is off.
11	RESET	input	A rising edge of a high pulse (typically 100 ns wide) resets the device, must be applied after power-up, and aborts a conversion or zeros the output registers if applied during a conversion or read.
12	RD/SCLK	input	Acts as the active-low parallel read control RD with CS in parallel mode, and as the serial clock input SCLK in serial mode.
13	CS	input	Active-low chip select frames the data transfer, and with RD low enables the parallel output bus or frames the serial read.
14	BUSY	output	Goes high after the CONVST A and CONVST B rising edges and falls when conversion data is latched into the output registers, so reads must finish before the BUSY falling edge.
15	FRSTDATA	output	Indicates when the V1 result is being read on the parallel or serial interface, and is three-state while CS is high.
16	DB0	tri_state	Parallel three-state data bit 0 outputs conversion bit DB2 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode.
17	DB1	tri_state	Parallel three-state data bit 1 outputs conversion bit DB3 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode.
18	DB2	tri_state	Parallel three-state data bit 2 outputs conversion bit DB4 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode.
19	DB3	tri_state	Parallel three-state data bit 3 outputs conversion bit DB5 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode.
20	DB4	tri_state	Parallel three-state data bit 4 outputs conversion bit DB6 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode.
21	DB5	tri_state	Parallel three-state data bit 5 outputs conversion bit DB7 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode.
22	DB6	tri_state	Parallel three-state data bit 6 outputs conversion bit DB8 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode.
23	VDRIVE	power_in	Logic supply of 2.3 V to 5 V sets the interface operating voltage and is nominally the host interface supply.
24	DB7/DOUTA	tri_state	Parallel data bit 7 outputs conversion bit DB9 when CS and RD are low, and functions as serial data output DOUTA when PAR/SER SEL is high.
25	DB8/DOUTB	tri_state	Parallel data bit 8 outputs conversion bit DB10 when CS and RD are low, and functions as serial data output DOUTB when PAR/SER SEL is high.
26	AGND	power_in	Analog ground is the reference point for all analog circuitry and should connect to the system AGND plane.
27	DB9	tri_state	Parallel three-state data bit 9 outputs conversion bit DB11 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode.
28	DB10	tri_state	Parallel three-state data bit 10 outputs conversion bit DB12 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode.
29	DB11	tri_state	Parallel three-state data bit 11 outputs conversion bit DB13 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode.
30	DB12	tri_state	Parallel three-state data bit 12 outputs conversion bit DB14 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode.
31	DB13	tri_state	Parallel three-state data bit 13 outputs conversion bit DB15 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode.
32	DB14	tri_state	Parallel three-state data bit 14 outputs conversion bit DB16 on the first RD pulse and DB0 on the second, and is tied to AGND in serial mode.
33	DB15	tri_state	Parallel three-state data bit 15 outputs conversion bit DB17 on the first RD pulse and DB1 on the second, and is tied to AGND in serial mode.
34	REF SELECT	input	A logic high selects and enables the internal 2.5 V reference, while a logic low disables it and requires an external 2.5 V reference on REFIN/REFOUT.
35	AGND	power_in	Analog ground is the reference point for all analog circuitry and should connect to the system AGND plane.
36	REGCAP	passive	Decoupling pin for the internal regulator output, which should be decoupled to AGND with a 1 µF capacitor and sits at 2.5 V to 2.7 V.
37	AVCC	power_in	Analog supply voltage of 4.75 V to 5.25 V feeds the front-end amplifiers and ADC core and should be decoupled to AGND.
38	AVCC	power_in	Analog supply voltage of 4.75 V to 5.25 V feeds the front-end amplifiers and ADC core and should be decoupled to AGND.
39	REGCAP	passive	Decoupling pin for the internal regulator output, which should be decoupled to AGND with a 1 µF capacitor and sits at 2.5 V to 2.7 V.
40	AGND	power_in	Analog ground is the reference point for all analog circuitry and should connect to the system AGND plane.
41	AGND	power_in	Analog ground is the reference point for all analog circuitry and should connect to the system AGND plane.
42	REFIN/REFOUT	bidirectional	Outputs the 2.5 V internal reference when REF SELECT is high or takes an external 2.5 V reference when it is low, and needs a 10 µF decoupling capacitor close to the REFGND pins.
43	REFGND	power_in	Reference ground pin that should be connected to AGND.
44	REFCAPA	passive	Reference buffer force/sense pin that must be tied to REFCAPB and decoupled to AGND with a low ESR 10 µF ceramic capacitor.
45	REFCAPB	passive	Reference buffer force/sense pin that must be tied to REFCAPA and decoupled to AGND with a low ESR 10 µF ceramic capacitor.
46	REFGND	power_in	Reference ground pin that should be connected to AGND.
47	AGND	power_in	Analog ground is the reference point for all analog circuitry and should connect to the system AGND plane.
48	AVCC	power_in	Analog supply voltage of 4.75 V to 5.25 V feeds the front-end amplifiers and ADC core and should be decoupled to AGND.
49	V1+	passive	Positive terminal of true differential analog input V1, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND.
50	V1-	passive	Negative terminal of true differential analog input V1, which should be 180° out of phase with V1+ and is limited to ±16.5 V to AGND.
51	V2+	passive	Positive terminal of true differential analog input V2, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND.
52	V2-	passive	Negative terminal of true differential analog input V2, which should be 180° out of phase with V2+ and is limited to ±16.5 V to AGND.
53	V3+	passive	Positive terminal of true differential analog input V3, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND.
54	V3-	passive	Negative terminal of true differential analog input V3, which should be 180° out of phase with V3+ and is limited to ±16.5 V to AGND.
55	V4+	passive	Positive terminal of true differential analog input V4, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND.
56	V4-	passive	Negative terminal of true differential analog input V4, which should be 180° out of phase with V4+ and is limited to ±16.5 V to AGND.
57	V5+	passive	Positive terminal of true differential analog input V5, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND.
58	V5-	passive	Negative terminal of true differential analog input V5, which should be 180° out of phase with V5+ and is limited to ±16.5 V to AGND.
59	V6+	passive	Positive terminal of true differential analog input V6, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND.
60	V6-	passive	Negative terminal of true differential analog input V6, which should be 180° out of phase with V6+ and is limited to ±16.5 V to AGND.
61	V7+	passive	Positive terminal of true differential analog input V7, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND.
62	V7-	passive	Negative terminal of true differential analog input V7, which should be 180° out of phase with V7+ and is limited to ±16.5 V to AGND.
63	V8+	passive	Positive terminal of true differential analog input V8, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND.
64	V8-	passive	Negative terminal of true differential analog input V8, which should be 180° out of phase with V8+ and is limited to ±16.5 V to AGND.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LQFP-64(10x10)
Category	Data Acquisition
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
AVCC analog supply voltage	AVCC	4.75		5.25	V		5
VDRIVE logic supply voltage	VDRIVE	2.3		5.25	V		5
Operating temperature range (B version)	TA	-40		85	°C	B version	11
Differential input voltage range, ±20 V	VIN	-20		20	V	RANGE = 1; ±20 V range	5
Differential input voltage range, ±10 V	VIN	-10		10	V	RANGE = 0; ±10 V range	5
Absolute voltage input, ±20 V range		-10		10	V	±20 V range, see Analog Input Clamp Protection section	5
Absolute voltage input, ±10 V range		-5		5	V	±10 V range, see Analog Input Clamp Protection section	5
Common-mode input range		-4		4	V		5
Reference input voltage range		2.475	2.5	2.525	V		5
DC leakage current (reference input)		-1		1	μA		5
Reference output voltage		2.49		2.505	V	REFIN/REFOUT	5
Reference temperature coefficient		-10		10	ppm/°C		5
Input current (logic inputs)	IIN	-2		2	μA		5
Output low voltage	VOL			0.2	V	ISINK = 100 μA	5
Normal mode (static) supply current	ITOTAL		16	22	mA	Digital inputs = 0 V or VDRIVE	5
Normal mode (operational) supply current	ITOTAL		20	28.5	mA	fSAMPLE = 200 kSPS	5
Standby mode supply current	ITOTAL		5	8	mA	Digital inputs = 0 V or VDRIVE	5
Shutdown mode supply current	ITOTAL		2	11	μA	Digital inputs = 0 V or VDRIVE	5
Normal mode (static) power dissipation			80	115.5	mW		6
Normal mode (operational) power dissipation			100	157	mW	fSAMPLE = 200 kSPS	6
Standby mode power dissipation			25	42	mW		6
Shutdown mode power dissipation			10	60.5	μW		6
AVCC to AGND	AVCC	-0.3		7	V		11
VDRIVE to AGND	VDRIVE	-0.3			V		11
Analog input voltage to AGND		-16.5		16.5	V		11
Digital input voltage to AGND		-0.3			V		11
Digital output voltage to AGND		-0.3			V		11
REFIN to AGND		-0.3			V		11
Input current to any pin except supplies		-10		10	mA		11
Storage temperature range		-65		150	°C		11
Junction temperature				150	°C		11
Pb/Sn temperature, soldering reflow				240	°C	Reflow 10 sec to 30 sec	11
Pb-free temperature, soldering reflow				260	°C		11
ESD, all pins except analog inputs				2	kV	All pins except analog inputs	11
ESD, analog input pins only				7	kV	Analog input pins only	11
Thermal resistance, junction-to-ambient, 64-lead LQFP	θJA		45		°C/W	Surface-mount device soldered in circuit board, 4-layer board	11
Thermal resistance, junction-to-case, 64-lead LQFP	θJC		11		°C/W		11

CAD (KiCad official)

Symbol: AD7609BSTZ
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: ad7609bstz-etched.step / ad7609bstz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7609bstz.step / ad7609bstz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (36 pp, sha256 8854f1daf3de5348, retrieved 2026-10-21, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# AD7609BSTZ

**Analog Devices** · ADCs/DACs - Special Purpose · LQFP-64(10x10)

AD7609BSTZ from Analog Devices, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AVCC | power_in | Analog supply voltage of 4.75 V to 5.25 V feeds the front-end amplifiers and ADC core and should be decoupled to AGND. |
| 2 | AGND | power_in | Analog ground is the reference point for all analog circuitry and all six AGND pins should connect to the system AGND plane. |
| 3 | OS 0 | input | Oversampling mode control bit OS 0 (LSB) selects the oversampling ratio as decoded in Table 9. |
| 4 | OS 1 | input | Oversampling mode control bit OS 1 selects the oversampling ratio as decoded in Table 9. |
| 5 | OS 2 | input | Oversampling mode control bit OS 2 (MSB) selects the oversampling ratio as decoded in Table 9. |
| 6 | PAR/SER SEL | input | A logic low selects the parallel interface and a logic high selects the serial interface. |
| 7 | STBY | input | Places the device into standby or shutdown mode depending on the RANGE pin state (Table 8), with standby keeping the reference, regulators and regulator buffers powered. |
| 8 | RANGE | input | A logic high sets the analog input range to ±20 V and a logic low sets it to ±10 V for all channels, and changing it during a conversion is not recommended. |
| 9 | CONVST A | input | A rising edge puts the track-and-hold for V1 to V4 (or all channels if tied to CONVST B) into hold to start conversions, and it is only usable separately when oversampling is off. |
| 10 | CONVST B | input | A rising edge puts the track-and-hold for V5 to V8 into hold when CONVST A and CONVST B are used separately, and it is only usable separately when oversampling is off. |
| 11 | RESET | input | A rising edge of a high pulse (typically 100 ns wide) resets the device, must be applied after power-up, and aborts a conversion or zeros the output registers if applied during a conversion or read. |
| 12 | RD/SCLK | input | Acts as the active-low parallel read control RD with CS in parallel mode, and as the serial clock input SCLK in serial mode. |
| 13 | CS | input | Active-low chip select frames the data transfer, and with RD low enables the parallel output bus or frames the serial read. |
| 14 | BUSY | output | Goes high after the CONVST A and CONVST B rising edges and falls when conversion data is latched into the output registers, so reads must finish before the BUSY falling edge. |
| 15 | FRSTDATA | output | Indicates when the V1 result is being read on the parallel or serial interface, and is three-state while CS is high. |
| 16 | DB0 | tri_state | Parallel three-state data bit 0 outputs conversion bit DB2 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode. |
| 17 | DB1 | tri_state | Parallel three-state data bit 1 outputs conversion bit DB3 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode. |
| 18 | DB2 | tri_state | Parallel three-state data bit 2 outputs conversion bit DB4 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode. |
| 19 | DB3 | tri_state | Parallel three-state data bit 3 outputs conversion bit DB5 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode. |
| 20 | DB4 | tri_state | Parallel three-state data bit 4 outputs conversion bit DB6 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode. |
| 21 | DB5 | tri_state | Parallel three-state data bit 5 outputs conversion bit DB7 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode. |
| 22 | DB6 | tri_state | Parallel three-state data bit 6 outputs conversion bit DB8 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode. |
| 23 | VDRIVE | power_in | Logic supply of 2.3 V to 5 V sets the interface operating voltage and is nominally the host interface supply. |
| 24 | DB7/DOUTA | tri_state | Parallel data bit 7 outputs conversion bit DB9 when CS and RD are low, and functions as serial data output DOUTA when PAR/SER SEL is high. |
| 25 | DB8/DOUTB | tri_state | Parallel data bit 8 outputs conversion bit DB10 when CS and RD are low, and functions as serial data output DOUTB when PAR/SER SEL is high. |
| 26 | AGND | power_in | Analog ground is the reference point for all analog circuitry and should connect to the system AGND plane. |
| 27 | DB9 | tri_state | Parallel three-state data bit 9 outputs conversion bit DB11 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode. |
| 28 | DB10 | tri_state | Parallel three-state data bit 10 outputs conversion bit DB12 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode. |
| 29 | DB11 | tri_state | Parallel three-state data bit 11 outputs conversion bit DB13 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode. |
| 30 | DB12 | tri_state | Parallel three-state data bit 12 outputs conversion bit DB14 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode. |
| 31 | DB13 | tri_state | Parallel three-state data bit 13 outputs conversion bit DB15 on the first RD pulse and 0 on the second, and is tied to AGND in serial mode. |
| 32 | DB14 | tri_state | Parallel three-state data bit 14 outputs conversion bit DB16 on the first RD pulse and DB0 on the second, and is tied to AGND in serial mode. |
| 33 | DB15 | tri_state | Parallel three-state data bit 15 outputs conversion bit DB17 on the first RD pulse and DB1 on the second, and is tied to AGND in serial mode. |
| 34 | REF SELECT | input | A logic high selects and enables the internal 2.5 V reference, while a logic low disables it and requires an external 2.5 V reference on REFIN/REFOUT. |
| 35 | AGND | power_in | Analog ground is the reference point for all analog circuitry and should connect to the system AGND plane. |
| 36 | REGCAP | passive | Decoupling pin for the internal regulator output, which should be decoupled to AGND with a 1 µF capacitor and sits at 2.5 V to 2.7 V. |
| 37 | AVCC | power_in | Analog supply voltage of 4.75 V to 5.25 V feeds the front-end amplifiers and ADC core and should be decoupled to AGND. |
| 38 | AVCC | power_in | Analog supply voltage of 4.75 V to 5.25 V feeds the front-end amplifiers and ADC core and should be decoupled to AGND. |
| 39 | REGCAP | passive | Decoupling pin for the internal regulator output, which should be decoupled to AGND with a 1 µF capacitor and sits at 2.5 V to 2.7 V. |
| 40 | AGND | power_in | Analog ground is the reference point for all analog circuitry and should connect to the system AGND plane. |
| 41 | AGND | power_in | Analog ground is the reference point for all analog circuitry and should connect to the system AGND plane. |
| 42 | REFIN/REFOUT | bidirectional | Outputs the 2.5 V internal reference when REF SELECT is high or takes an external 2.5 V reference when it is low, and needs a 10 µF decoupling capacitor close to the REFGND pins. |
| 43 | REFGND | power_in | Reference ground pin that should be connected to AGND. |
| 44 | REFCAPA | passive | Reference buffer force/sense pin that must be tied to REFCAPB and decoupled to AGND with a low ESR 10 µF ceramic capacitor. |
| 45 | REFCAPB | passive | Reference buffer force/sense pin that must be tied to REFCAPA and decoupled to AGND with a low ESR 10 µF ceramic capacitor. |
| 46 | REFGND | power_in | Reference ground pin that should be connected to AGND. |
| 47 | AGND | power_in | Analog ground is the reference point for all analog circuitry and should connect to the system AGND plane. |
| 48 | AVCC | power_in | Analog supply voltage of 4.75 V to 5.25 V feeds the front-end amplifiers and ADC core and should be decoupled to AGND. |
| 49 | V1+ | passive | Positive terminal of true differential analog input V1, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND. |
| 50 | V1- | passive | Negative terminal of true differential analog input V1, which should be 180° out of phase with V1+ and is limited to ±16.5 V to AGND. |
| 51 | V2+ | passive | Positive terminal of true differential analog input V2, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND. |
| 52 | V2- | passive | Negative terminal of true differential analog input V2, which should be 180° out of phase with V2+ and is limited to ±16.5 V to AGND. |
| 53 | V3+ | passive | Positive terminal of true differential analog input V3, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND. |
| 54 | V3- | passive | Negative terminal of true differential analog input V3, which should be 180° out of phase with V3+ and is limited to ±16.5 V to AGND. |
| 55 | V4+ | passive | Positive terminal of true differential analog input V4, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND. |
| 56 | V4- | passive | Negative terminal of true differential analog input V4, which should be 180° out of phase with V4+ and is limited to ±16.5 V to AGND. |
| 57 | V5+ | passive | Positive terminal of true differential analog input V5, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND. |
| 58 | V5- | passive | Negative terminal of true differential analog input V5, which should be 180° out of phase with V5+ and is limited to ±16.5 V to AGND. |
| 59 | V6+ | passive | Positive terminal of true differential analog input V6, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND. |
| 60 | V6- | passive | Negative terminal of true differential analog input V6, which should be 180° out of phase with V6+ and is limited to ±16.5 V to AGND. |
| 61 | V7+ | passive | Positive terminal of true differential analog input V7, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND. |
| 62 | V7- | passive | Negative terminal of true differential analog input V7, which should be 180° out of phase with V7+ and is limited to ±16.5 V to AGND. |
| 63 | V8+ | passive | Positive terminal of true differential analog input V8, with range set by the RANGE pin and an absolute maximum of ±16.5 V to AGND. |
| 64 | V8- | passive | Negative terminal of true differential analog input V8, which should be 180° out of phase with V8+ and is limited to ±16.5 V to AGND. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LQFP-64(10x10) |
| Category | Data Acquisition |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| AVCC analog supply voltage | AVCC | 4.75 |  | 5.25 | V |  | 5 |
| VDRIVE logic supply voltage | VDRIVE | 2.3 |  | 5.25 | V |  | 5 |
| Operating temperature range (B version) | TA | -40 |  | 85 | °C | B version | 11 |
| Differential input voltage range, ±20 V | VIN | -20 |  | 20 | V | RANGE = 1; ±20 V range | 5 |
| Differential input voltage range, ±10 V | VIN | -10 |  | 10 | V | RANGE = 0; ±10 V range | 5 |
| Absolute voltage input, ±20 V range |  | -10 |  | 10 | V | ±20 V range, see Analog Input Clamp Protection section | 5 |
| Absolute voltage input, ±10 V range |  | -5 |  | 5 | V | ±10 V range, see Analog Input Clamp Protection section | 5 |
| Common-mode input range |  | -4 |  | 4 | V |  | 5 |
| Reference input voltage range |  | 2.475 | 2.5 | 2.525 | V |  | 5 |
| DC leakage current (reference input) |  | -1 |  | 1 | μA |  | 5 |
| Reference output voltage |  | 2.49 |  | 2.505 | V | REFIN/REFOUT | 5 |
| Reference temperature coefficient |  | -10 |  | 10 | ppm/°C |  | 5 |
| Input current (logic inputs) | IIN | -2 |  | 2 | μA |  | 5 |
| Output low voltage | VOL |  |  | 0.2 | V | ISINK = 100 μA | 5 |
| Normal mode (static) supply current | ITOTAL |  | 16 | 22 | mA | Digital inputs = 0 V or VDRIVE | 5 |
| Normal mode (operational) supply current | ITOTAL |  | 20 | 28.5 | mA | fSAMPLE = 200 kSPS | 5 |
| Standby mode supply current | ITOTAL |  | 5 | 8 | mA | Digital inputs = 0 V or VDRIVE | 5 |
| Shutdown mode supply current | ITOTAL |  | 2 | 11 | μA | Digital inputs = 0 V or VDRIVE | 5 |
| Normal mode (static) power dissipation |  |  | 80 | 115.5 | mW |  | 6 |
| Normal mode (operational) power dissipation |  |  | 100 | 157 | mW | fSAMPLE = 200 kSPS | 6 |
| Standby mode power dissipation |  |  | 25 | 42 | mW |  | 6 |
| Shutdown mode power dissipation |  |  | 10 | 60.5 | μW |  | 6 |
| AVCC to AGND | AVCC | -0.3 |  | 7 | V |  | 11 |
| VDRIVE to AGND | VDRIVE | -0.3 |  |  | V |  | 11 |
| Analog input voltage to AGND |  | -16.5 |  | 16.5 | V |  | 11 |
| Digital input voltage to AGND |  | -0.3 |  |  | V |  | 11 |
| Digital output voltage to AGND |  | -0.3 |  |  | V |  | 11 |
| REFIN to AGND |  | -0.3 |  |  | V |  | 11 |
| Input current to any pin except supplies |  | -10 |  | 10 | mA |  | 11 |
| Storage temperature range |  | -65 |  | 150 | °C |  | 11 |
| Junction temperature |  |  |  | 150 | °C |  | 11 |
| Pb/Sn temperature, soldering reflow |  |  |  | 240 | °C | Reflow 10 sec to 30 sec | 11 |
| Pb-free temperature, soldering reflow |  |  |  | 260 | °C |  | 11 |
| ESD, all pins except analog inputs |  |  |  | 2 | kV | All pins except analog inputs | 11 |
| ESD, analog input pins only |  |  |  | 7 | kV | Analog input pins only | 11 |
| Thermal resistance, junction-to-ambient, 64-lead LQFP | θJA |  | 45 |  | °C/W | Surface-mount device soldered in circuit board, 4-layer board | 11 |
| Thermal resistance, junction-to-case, 64-lead LQFP | θJC |  | 11 |  | °C/W |  | 11 |

## CAD (KiCad official)

- Symbol: `AD7609BSTZ`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `ad7609bstz-etched.step` / `ad7609bstz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7609bstz.step` / `ad7609bstz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8758079679012458496) (36 pp, sha256 `8854f1daf3de5348`, retrieved 2026-10-21, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad7609bstz-datasheet.pdf)