component

AD7609BSTZ-RL

Public Made by Adom

by adom

Analog Devices ADCs/DACs - Special Purpose, LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata acquisitionad7609bstz-rlfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers ad7609bstz-rl: viewers · Ray 5d ago
ad7609bstz-rl-etched.glb Publish 0.1.0 · Ray 5d ago
ad7609bstz-rl-etched.step ad7609bstz-rl: factory component page (tier=lcsc) · Ray 5d ago
ad7609bstz-rl-hero.glb ad7609bstz-rl: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
ad7609bstz-rl-hero.overlay.json Publish 0.1.0 · Ray 5d ago
ad7609bstz-rl.glb Publish 0.1.0 · Ray 5d ago
ad7609bstz-rl.kicad_mod Publish 0.1.0 · Ray 5d ago
ad7609bstz-rl.kicad_sym Publish 0.1.0 · Ray 5d ago
ad7609bstz-rl.lbr Publish 0.1.0 · Ray 5d ago
ad7609bstz-rl.step Publish 0.1.0 · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago

AD7609BSTZ-RL

Analog Devices · ADCs/DACs - Special Purpose · LQFP-64(10x10)

AD7609BSTZ-RL from Analog Devices, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVCC power_in Analog supply, 4.75 V to 5.25 V, powering the front-end amplifiers and ADC core; decouple to AGND.
2 AGND power_in Analog ground reference for all analog circuitry and analog inputs; all six AGND pins must connect to the system AGND plane.
3 OS0 input Oversampling rate select, LSB of OS[2:0], latched on the BUSY falling edge to set the next conversion's oversampling rate.
4 OS1 input Oversampling rate select, middle bit of OS[2:0], latched on the BUSY falling edge to set the next conversion's oversampling rate.
5 OS2 input Oversampling rate select, MSB of OS[2:0], latched on the BUSY falling edge to set the next conversion's oversampling rate.
6 PAR/SER SEL input Interface select: low selects the parallel interface, high selects the serial interface.
7 STBY input Power-down control; with RANGE set low it selects standby (RANGE high) or shutdown (RANGE low) mode.
8 RANGE input Analog input range select for all channels: high gives ±10 V, low gives ±5 V; avoid changing it during conversion.
9 CONVST A input Conversion start input A; tie to CONVST B for simultaneous sampling of all eight channels, and ignored while BUSY is high.
10 CONVST B input Conversion start input B; tie to CONVST A for simultaneous sampling, or pulse separately (only without oversampling) to sample V1-V4 and V5-V8 in two groups.
11 RESET input Active-high reset; a rising edge resets the AD7609, which must be reset after power-up and after leaving shutdown.
12 RD/SCLK input Parallel read strobe RD in parallel mode, or serial clock SCLK in serial mode.
13 CS input Active-low chip select that enables the data frame transfer on the parallel or serial interface.
14 BUSY output Goes high after CONVST rises and stays high until all channel conversions complete; its falling edge signals that data is ready to read.
15 FRSTDATA output Indicates when channel V1 result is on the interface during readback; tri-state when CS is high.
16 DB0 tri_state Tri-state parallel data output bit 0; tie to AGND when the serial interface is selected.
17 DB1 tri_state Tri-state parallel data output bit 1; tie to AGND when the serial interface is selected.
18 DB2 tri_state Tri-state parallel data output bit 2; tie to AGND when the serial interface is selected.
19 DB3 tri_state Tri-state parallel data output bit 3; tie to AGND when the serial interface is selected.
20 DB4 tri_state Tri-state parallel data output bit 4; tie to AGND when the serial interface is selected.
21 DB5 tri_state Tri-state parallel data output bit 5; tie to AGND when the serial interface is selected.
22 DB6 tri_state Tri-state parallel data output bit 6; tie to AGND when the serial interface is selected.
23 VDRIVE power_in Logic supply, 2.3 V to 5 V, sets the logic interface voltage and should match the host (DSP/FPGA) supply.
24 DB7/DOUTA tri_state Parallel data bit 7 in parallel mode; serial data output DOUTA (channels V1-V4) in serial mode.
25 DB8/DOUTB tri_state Parallel data bit 8 in parallel mode; serial data output DOUTB (channels V5-V8) in serial mode.
26 AGND power_in Analog ground pin, connected to the system AGND plane.
27 DB9 tri_state Tri-state parallel data output bit 9; tie to AGND when the serial interface is selected.
28 DB10 tri_state Tri-state parallel data output bit 10; tie to AGND when the serial interface is selected.
29 DB11 tri_state Tri-state parallel data output bit 11; tie to AGND when the serial interface is selected.
30 DB12 tri_state Tri-state parallel data output bit 12; tie to AGND when the serial interface is selected.
31 DB13 tri_state Tri-state parallel data output bit 13; tie to AGND when the serial interface is selected.
32 DB14 tri_state Tri-state parallel data output bit 14; tie to AGND when the serial interface is selected.
33 DB15 tri_state Tri-state parallel data output bit 15; tie to AGND when the serial interface is selected.
34 REF SELECT input Reference select: high enables the internal 2.5 V reference, low disables it and requires an external 2.5 V reference on REFIN/REFOUT.
35 AGND power_in Analog ground pin, connected to the system AGND plane.
36 REGCAP power_out Internal regulator output, 2.5 V to 2.7 V; decouple to AGND with 1 µF.
37 AVCC power_in Analog supply, 4.75 V to 5.25 V; decouple to AGND (may share decoupling with pin 38).
38 AVCC power_in Analog supply, 4.75 V to 5.25 V; decouple to AGND.
39 REGCAP power_out Internal regulator output, 2.5 V to 2.7 V; decouple to AGND with 1 µF.
40 AGND power_in Analog ground pin, connected to the system AGND plane.
41 AGND power_in Analog ground pin, connected to the system AGND plane.
42 REFIN/REFOUT bidirectional Reference output of 2.5 V when REF SELECT is high, or 2.5 V external reference input when REF SELECT is low; decouple with 10 µF to REFGND.
43 REFGND power_in Reference ground pin, which must be connected to AGND.
44 REFCAPA passive Reference buffer force/sense pin; must be shorted to REFCAPB and decoupled to REFGND with a low-ESR 10 µF ceramic capacitor.
45 REFCAPB passive Reference buffer force/sense pin; must be shorted to REFCAPA and decoupled to REFGND with a low-ESR 10 µF ceramic capacitor.
46 REFGND power_in Reference ground pin, which must be connected to AGND.
47 AGND power_in Analog ground pin, connected to the system AGND plane.
48 AVCC power_in Analog supply, 4.75 V to 5.25 V; decouple to AGND.
49 V1+ input Positive true-differential analog input for channel 1; ±10 V or ±5 V range set by RANGE.
50 V1- input Negative true-differential analog input for channel 1; must be 180° out of phase with V1+.
51 V2+ input Positive true-differential analog input for channel 2; ±10 V or ±5 V range set by RANGE.
52 V2- input Negative true-differential analog input for channel 2; must be 180° out of phase with V2+.
53 V3+ input Positive true-differential analog input for channel 3; ±10 V or ±5 V range set by RANGE.
54 V3- input Negative true-differential analog input for channel 3; must be 180° out of phase with V3+.
55 V4+ input Positive true-differential analog input for channel 4; ±10 V or ±5 V range set by RANGE.
56 V4- input Negative true-differential analog input for channel 4; must be 180° out of phase with V4+.
57 V5+ input Positive true-differential analog input for channel 5; ±10 V or ±5 V range set by RANGE.
58 V5- input Negative true-differential analog input for channel 5; must be 180° out of phase with V5+.
59 V6+ input Positive true-differential analog input for channel 6; ±10 V or ±5 V range set by RANGE.
60 V6- input Negative true-differential analog input for channel 6; must be 180° out of phase with V6+.
61 V7+ input Positive true-differential analog input for channel 7; ±10 V or ±5 V range set by RANGE.
62 V7- input Negative true-differential analog input for channel 7; must be 180° out of phase with V7+.
63 V8+ input Positive true-differential analog input for channel 8; ±10 V or ±5 V range set by RANGE.
64 V8- input Negative true-differential analog input for channel 8; must be 180° out of phase with V8+.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LQFP-64(10x10)
Category Data Acquisition
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Signal-to-noise ratio, 16x oversampling, ±10 V range, fIN=160 Hz SNR 98 101 dB 16倍过采样；±10 V范围；fIN=160 Hz 4
Signal-to-noise ratio, no oversampling, ±10 V range SNR 90 91 dB 无过采样；±10 V范围 4
Signal-to-noise ratio, no oversampling, ±5 V range SNR 89.5 90.5 dB 无过采样；±5 V范围 4
Signal-to-noise and distortion, ±10 V range SINAD 89.5 91 dB 无过采样; ±10 V范围 4
Signal-to-noise and distortion, ±5 V range SINAD 89 90 dB 无过采样; ±5 V范围 4
Total harmonic distortion, ±10 V range THD -107 -97 dB 无过采样; ±10 V范围 4
Total harmonic distortion, ±5 V range THD -110 -96 dB 无过采样; ±5 V范围 4
Integral nonlinearity INL -7.5 7.5 LSB 4
Differential nonlinearity DNL -0.99 2 LSB 4
Total unadjusted error, ±10 V range TUE -10 10 LSB ±10 V范围 4
Total unadjusted error, ±5 V range TUE -90 90 LSB ±5 V范围 4
Positive full-scale error PFS -140 140 LSB 外部基准电压源 4
Positive full-scale error PFS -40 40 LSB 内部基准电压源 4
Positive full-scale error drift PFS drift -2 2 ppm/°C 外部基准电压源 4
Positive full-scale error matching, ±10 V range PFS match 12 80 LSB ±10 V范围 4
Positive full-scale error matching, ±5 V range PFS match 40 100 LSB ±5 V范围 4
Negative full-scale error NFS -140 140 LSB 外部基准电压源 4
Negative full-scale error NFS -40 40 LSB 内部基准电压源 4
Negative full-scale error drift NFS drift -4 4 ppm/°C 外部基准电压源 4
Negative full-scale error matching, ±10 V range NFS match 12 80 LSB ±10 V范围 4
Bipolar zero-code error, ±10 V range -24 24 LSB ±10 V范围 4
Bipolar zero-code error, ±5 V range -48 48 LSB ±5 V范围 4
Differential analog input voltage range VIN -20 20 V VIN = Vx+ − (Vx−); RANGE = 1; ±10 V 5
Differential analog input voltage range VIN -10 10 V VIN = Vx+ − (Vx−); RANGE = 0; ±5 V 5
Common-mode input range -4 4 V 5
Reference input voltage range VREF 2.475 2.5 2.525 V 基准输入电压范围 5
Reference output voltage REFIN/REFOUT 2.49 2.505 V 基准输出电压 REFIN/REFOUT 5
Input current IIN -2 2 µA 逻辑输入 5
Logic output low voltage VOL 0.2 V ISINK = 100 µA 5
Total supply current, normal mode static ITOTAL 16 22 mA 数字输入 = 0 V或VDRIVE；正常模式(静态) 5
Total supply current, normal mode operating at 200 kSPS ITOTAL 20 28.5 mA 数字输入 = 0 V或VDRIVE；正常模式(工作状态) fSAMPLE = 200 kSPS 5
Total supply current, standby mode ITOTAL 5 8 mA 数字输入 = 0 V或VDRIVE；待机模式 5
Total supply current, shutdown mode ITOTAL 2 11 µA 数字输入 = 0 V或VDRIVE；关断模式 5
Conversion time, oversampling off tCONV 3.45 4 4.15 µs 过采样关闭；转换时间 7
Conversion-to-next-conversion delay between CONVST A and CONVST B t5 0.5 ms CONVST A/CONVST B上升沿之间最大容许延迟时间 7
RESET high pulse width tRESET 50 ns RESET高电平脉冲宽度 7
Shortest CONVST x low pulse t2 25 ns 最短CONVST x低电平脉冲 7
Analog supply voltage AVCC AVCC 4.75 5.25 V 5
Logic supply voltage VDRIVE VDRIVE 2.3 5.25 V 5
AVCC to AGND AVCC -0.3 7 V 11
Analog input voltage to AGND -16.5 16.5 V 模拟输入电压至AGND 11
Input current to any pin except supplies -10 10 mA 除电源外的任何引脚 11
Storage temperature range -65 150 °C 存储温度范围 11
Junction temperature 150 °C 结温 11
Lead soldering temperature, reflow 10 s to 30 s 240 °C 铅锡焊接温度，回流焊(10秒至30秒) 11
Junction-to-ambient thermal resistance, 64-lead LQFP θJA 45 °C/W 4层电路板，表面贴装封装 11
Junction-to-case thermal resistance, 64-lead LQFP θJC 11 °C/W 64引脚 LQFP 11
Spurious-free dynamic range SFDR -108 dB 4
Intermodulation distortion, third-order term IMD -106 dB fa = 1 kHz，fb = 1.1 kHz；三阶项 4
Channel-to-channel isolation -95 dB 未选中通道的fIN高达160 kHz 4
Full-power bandwidth, −3 dB, ±10 V range 32 kHz −3 dB，±10 V范围 4
Bandwidth, −0.1 dB, ±10 V range 13 kHz −0.1 dB， ±10 V范围 4
Input current, 10 V input 5.4 µA 10 V，见图28 5
Input current, 5 V input 2.5 µA 5 V，见图28 5
Analog input capacitance 5 pF 输入电容 5
Analog input impedance 1 MΩ 输入阻抗 5
Wake-up time from standby tWAKE-UP STANDBY 100 µs STBY上升沿到CONVST x上升沿；从待机模式上电的时间 7

CAD (KiCad official)

  • Symbol: AD7609BSTZ-RL
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ad7609bstz-rl-etched.step / ad7609bstz-rl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7609bstz-rl.step / ad7609bstz-rl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (36 pp, sha256 7dfa0a6742ce7a5b, retrieved 2026-10-20, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF