component
AD7606C-18BSTZ-RL
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownAD7606C-18BSTZ-RL
Analog Devices · Analog To Digital Converters (ADC) · LQFP-64(10x10)
AD7606C-18BSTZ-RL from Analog Devices, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AVCC | power_in | Analog supply voltage of 4.75 V to 5.25 V applied to the internal front-end amplifiers and ADC core; decouple to AGND. |
| 2 | AGND | power_in | Analog ground reference for all analog circuitry; all six AGND pins must connect to the system AGND plane. |
| 3 | OS0 | input | Oversampling mode pin 0 selecting the oversampling ratio; software mode is enabled only when OS0 to OS2 are all tied high. |
| 4 | OS1 | input | Oversampling mode pin 1 selecting the oversampling ratio; software mode is enabled only when OS0 to OS2 are all tied high. |
| 5 | OS2 | input | Oversampling mode pin 2 selecting the oversampling ratio; software mode is enabled only when OS0 to OS2 are all tied high. |
| 6 | PAR/SER SEL | input | Interface select: logic low selects the parallel interface and logic high selects the serial interface. |
| 7 | STBY | input | In hardware mode, combined with RANGE to select standby or shutdown power-down; ignored in software mode and recommended to be tied high. |
| 8 | RANGE | input | In hardware mode selects the analog input range (Table 10) or the power-down mode when STBY is low; must be tied high or low in software mode. |
| 9 | CONVST | input | A low-to-high transition samples the analog input on all eight SAR ADCs, and in software mode the pin can instead serve as an external oversampling clock. |
| 10 | WR | input | Active-low parallel write control used only in software mode for register writes; it has no function in hardware mode and may be tied high, tied low, or shorted to CONVST. |
| 11 | RESET | input | Active-high reset where the pulse length selects full or partial reset, and a full reset pulse is recommended after power-up. |
| 12 | RD/SCLK | input | Parallel read control (RD) when the parallel interface is selected, or serial clock input (SCLK) when the serial interface is selected. |
| 13 | CS | input | Active-low chip select for ADC data reads and register reads and writes in both the serial and parallel interfaces. |
| 14 | BUSY | output | Goes high with the CONVST rising edge and remains high until the conversion process for all channels is complete. |
| 15 | FRSTDATA | output | Indicates when the first channel V1 is being read back on the parallel or serial interface, and is three-stated when CS is high. |
| 16 | DB2 | bidirectional | Parallel data bit 2 (three-state parallel input/output); tie to AGND when the serial interface is used. |
| 17 | DB3 | bidirectional | Parallel data bit 3 (three-state parallel input/output); tie to AGND when the serial interface is used. |
| 18 | DB4 | bidirectional | Parallel data bit 4 (three-state parallel input/output); tie to AGND when the serial interface is used. |
| 19 | DB5/DOUTE | bidirectional | Parallel data bit 5 in parallel mode; serial data output DOUTE only in 8 DOUTx software mode, otherwise leave unconnected. |
| 20 | DB6/DOUTF | bidirectional | Parallel data bit 6 in parallel mode; serial data output DOUTF only in 8 DOUTx software mode, otherwise leave unconnected. |
| 21 | DB7/DOUTG | bidirectional | Parallel data bit 7 in parallel mode; serial data output DOUTG only in 8 DOUTx software mode, otherwise leave unconnected. |
| 22 | DB8/DOUTH | bidirectional | Parallel data bit 8 in parallel mode; serial data output DOUTH only in 8 DOUTx software mode, otherwise leave unconnected. |
| 23 | VDRIVE | power_in | Logic supply of 1.71 V to 5.25 V that sets the operating voltage of the digital interface and is nominally the host DSP/FPGA supply. |
| 24 | DB9/DOUTA | bidirectional | Parallel data bit 9 (MSB of register data in register mode); serial data output DOUTA when the serial interface is used. |
| 25 | DB10/DOUTB | bidirectional | Parallel data bit 10 (ADD0 in register mode); serial data output DOUTB, used only when 2, 4, or 8 DOUTx mode is selected, otherwise leave unconnected. |
| 26 | AGND | power_in | Analog ground reference for all analog circuitry; must connect to the system AGND plane. |
| 27 | DB11/DOUTC | bidirectional | Parallel data bit 11 (ADD1 in register mode); serial data output DOUTC only in software mode with the 4 or 8 DOUTx option, otherwise leave unconnected. |
| 28 | DB12/DOUTD | bidirectional | Parallel data bit 12 (ADD2 in register mode); serial data output DOUTD only in software mode with the 4 or 8 DOUTx option, otherwise leave unconnected. |
| 29 | DB13/SDI | bidirectional | Parallel data bit 13 (ADD3 in register mode); serial data input SDI when the serial interface is used in software mode. |
| 30 | DB14 | bidirectional | Parallel data bit 14 (ADD4 in register mode); tie to AGND when the serial interface is used. |
| 31 | DB15 | bidirectional | Parallel data bit 15 (ADD5 in register mode); tie to AGND when the serial interface is used. |
| 32 | DB16/DB0 | bidirectional | Parallel data bit 16 on the first read frame and DB0 on the second read frame (ADD6 in register mode); tie to AGND when the serial interface is used. |
| 33 | DB17/DB1 | bidirectional | Parallel data bit 17 on the first read frame and DB1 on the second read frame (R/W in register mode); tie to AGND when the serial interface is used. |
| 34 | REF SELECT | input | Logic high selects and enables the internal 2.5 V reference; logic low disables it and requires an external 2.5 V reference on REFIN. |
| 35 | AGND | power_in | Analog ground reference for all analog circuitry; must connect to the system AGND plane. |
| 36 | REGCAP | power_out | Decoupling pin for the 1.9 V internal ALDO/DLDO regulator output, to be decoupled to AGND with a separate 1 µF capacitor; voltage 1.875 V to 1.93 V. |
| 37 | AVCC | power_in | Analog supply voltage of 4.75 V to 5.25 V; decouple to AGND. |
| 38 | AVCC | power_in | Analog supply voltage of 4.75 V to 5.25 V; decouple to AGND. |
| 39 | REGCAP | power_out | Decoupling pin for the 1.9 V internal ALDO/DLDO regulator output, to be decoupled to AGND with a separate 1 µF capacitor; voltage 1.875 V to 1.93 V. |
| 40 | AGND | power_in | Analog ground reference for all analog circuitry; must connect to the system AGND plane. |
| 41 | AGND | power_in | Analog ground reference for all analog circuitry; must connect to the system AGND plane. |
| 42 | REFIN/REFOUT | bidirectional | Internal 2.5 V reference output when REF SELECT is high, or external 2.5 V reference input when REF SELECT is low; a 100 nF capacitor is required from this pin to ground near REFGND. |
| 43 | REFGND | power_in | Reference ground pin that must be connected to AGND. |
| 44 | REFCAPA | power_out | Reference buffer output force/sense pin that must be connected to REFCAPB and decoupled to AGND with a low-ESR 10 µF ceramic capacitor; typically 4.4 V. |
| 45 | REFCAPB | power_out | Reference buffer output force/sense pin that must be connected to REFCAPA and decoupled to AGND with a low-ESR 10 µF ceramic capacitor; typically 4.4 V. |
| 46 | REFGND | power_in | Reference ground pin that must be connected to AGND. |
| 47 | AGND | power_in | Analog ground reference for all analog circuitry; must connect to the system AGND plane. |
| 48 | AVCC | power_in | Analog supply voltage of 4.75 V to 5.25 V; decouple to AGND. |
| 49 | V1+ | input | Channel 1 positive analog input; the analog input voltage is rated to ±21 V with respect to AGND. |
| 50 | V1- | input | Channel 1 negative analog input; the analog input voltage is rated to ±21 V with respect to AGND. |
| 51 | V2+ | input | Channel 2 positive analog input; the analog input voltage is rated to ±21 V with respect to AGND. |
| 52 | V2- | input | Channel 2 negative analog input; the analog input voltage is rated to ±21 V with respect to AGND. |
| 53 | V3+ | input | Channel 3 positive analog input; the analog input voltage is rated to ±21 V with respect to AGND. |
| 54 | V3- | input | Channel 3 negative analog input; the analog input voltage is rated to ±21 V with respect to AGND. |
| 55 | V4+ | input | Channel 4 positive analog input; the analog input voltage is rated to ±21 V with respect to AGND. |
| 56 | V4- | input | Channel 4 negative analog input; the analog input voltage is rated to ±21 V with respect to AGND. |
| 57 | V5+ | input | Channel 5 positive analog input; the analog input voltage is rated to ±21 V with respect to AGND. |
| 58 | V5- | input | Channel 5 negative analog input; the analog input voltage is rated to ±21 V with respect to AGND. |
| 59 | V6+ | input | Channel 6 positive analog input; the analog input voltage is rated to ±21 V with respect to AGND. |
| 60 | V6- | input | Channel 6 negative analog input; the analog input voltage is rated to ±21 V with respect to AGND. |
| 61 | V7+ | input | Channel 7 positive analog input; the analog input voltage is rated to ±21 V with respect to AGND. |
| 62 | V7- | input | Channel 7 negative analog input; the analog input voltage is rated to ±21 V with respect to AGND. |
| 63 | V8+ | input | Channel 8 positive analog input; the analog input voltage is rated to ±21 V with respect to AGND. |
| 64 | V8- | input | Channel 8 negative analog input; the analog input voltage is rated to ±21 V with respect to AGND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LQFP-64(10x10) |
| Category | Data Acquisition |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Differential Nonlinearity (DNL) | -0.99 | 0.5 | 0.99 | LSB | 5 | ||
| Integral Nonlinearity (INL) | -7.5 | 2 | 7.5 | LSB | Bipolar input ranges | 5 | |
| Total Unadjusted Error (TUE), external reference | -130 | 25 | 130 | LSB | External reference | 5 | |
| Total Unadjusted Error (TUE), external reference ±2.5 V range | -180 | 25 | 180 | LSB | External reference, ±2.5 V range | 5 | |
| Total Unadjusted Error (TUE), unipolar input ranges | -280 | 60 | 280 | LSB | Unipolar input ranges | 5 | |
| Positive Full-Scale (PFS) and Negative Full-Scale (NFS) Error | -120 | 20 | 120 | LSB | Bipolar ranges | 5 | |
| PFS and NFS Error Drift | -3 | 0.5 | 3 | ppm/°C | 5 | ||
| PFS and NFS Error Matching | 15 | 60 | LSB | 5 | |||
| Bipolar Zero Code Error | -160 | 10 | 160 | LSB | 2.5 V range | 5 | |
| Bipolar Zero Code Error | -80 | 10 | 80 | LSB | All other input ranges | 5 | |
| Bipolar Zero Code Error Drift | -5 | 2 | 5 | ppm/°C | 2.5 V range | 5 | |
| Bipolar Zero Code Error Drift | -2.5 | 0.5 | 2.5 | ppm/°C | All other input ranges | 5 | |
| Bipolar Zero Code Error Matching | 20 | 90 | LSB | 5 | |||
| Unipolar FS Error | -240 | 40 | 240 | LSB | Unipolar ranges | 5 | |
| Unipolar FS Error Drift | -7 | 1 | 7 | ppm/°C | Unipolar ranges | 5 | |
| Unipolar FS Error Matching | 20 | 160 | LSB | Unipolar ranges | 5 | ||
| Zero Scale Error | -200 | 40 | 200 | LSB | Unipolar ranges | 5 | |
| Zero Scale Error Drift | -7 | 2.5 | 7 | ppm/°C | Unipolar ranges | 5 | |
| Zero Scale Error Matching | 20 | 160 | LSB | Unipolar ranges | 5 | ||
| PFS and NFS Calibration Range | 1 | 64 | kΩ | Series resistor in front of the Vx+ and Vx− inputs | 5 | ||
| Offset Calibration Range | 1 | 512 | LSB | 5 | |||
| Phase Calibration Range | 1 | 255 | µs | 5 | |||
| PFS and NFS Error | -60 | 60 | LSB | After gain calibration | 5 | ||
| Offset Error | -2 | 2 | LSB | After offset calibration | 5 | ||
| Phase Error | -1 | 1 | µs | After phase calibration | 5 | ||
| Input Impedance (RIN) | RIN | 1 | 1.2 | MΩ | 6 | ||
| Input Impedance Drift | RIN | -25 | 1 | 25 | ppm/°C | 6 | |
| Input Current (IIN), logic inputs | IIN | -1 | 1 | µA | 6 | ||
| Reference Input Voltage | 2.495 | 2.5 | 2.505 | V | External reference | 6 | |
| Reference Output Voltage | 2.4975 | 2.5 | 2.5025 | V | Internal reference, TA = 25°C | 6 | |
| Reference Temperature Coefficient | -10 | 3 | 10 | ppm/°C | 6 | ||
| Reference Voltage to the ADC (REFCAPA, REFCAPB) | 4.39 | 4.41 | V | 6 | |||
| Output Low Voltage (VOL) | VOL | 0.2 | V | Sink current (ISINK) = 100 µA | 6 | ||
| Floating State Leakage Current | -1 | 1 | µA | 6 | |||
| Absolute Maximum AVCC to AGND | AVCC | -0.3 | 6.5 | V | 11 | ||
| Analog Input Voltage to AGND | -21 | 21 | V | 11 | |||
| Input Current to Any Pin Except Supplies | -10 | 10 | mA | Except supplies | 11 | ||
| Operating Range | TA | -40 | 125 | °C | 11 | ||
| Storage Range | -65 | 150 | °C | 11 | |||
| Junction Temperature | 150 | °C | 11 | ||||
| Pb/Sn Soldering Reflow | 240 | °C | 10 sec to 30 sec | 11 | |||
| Pb-Free Soldering Reflow | 260 | °C | 11 | ||||
| AVCC Analog Supply Voltage | AVCC | 4.75 | 5 | 5.25 | V | 6 | |
| VDRIVE Supply Voltage | VDRIVE | 1.71 | 5.25 | V | 6 | ||
| AVCC Current, Normal Mode (Static) | IAVCC | 9 | 11 | mA | Normal mode (static) | 6 | |
| AVCC Current, Normal Mode (Operational) | IAVCC | 45 | 50 | mA | Normal mode (operational), fSAMPLE = 1 MSPS | 6 | |
| AVCC Current, Normal Mode (Operational) | IAVCC | 8.5 | 10 | mA | Normal mode (operational), fSAMPLE = 10 kSPS | 6 | |
| AVCC Current, Standby Mode | IAVCC | 5 | 6 | mA | Standby | 6 | |
| AVCC Current, Shutdown Mode | IAVCC | 0.5 | 5 | µA | Shutdown mode | 6 | |
| VDRIVE Current, Normal Mode (Static) | IVDRIVE | 2.8 | 5 | µA | Normal mode (static) | 6 | |
| VDRIVE Current, Normal Mode (Operational) | IVDRIVE | 1.8 | 1.9 | mA | Normal mode (operational), fSAMPLE = 1 MSPS | 6 | |
| VDRIVE Current, Normal Mode (Operational) | IVDRIVE | 21 | 24 | µA | Normal mode (operational), fSAMPLE = 10 kSPS | 6 | |
| VDRIVE Current, Standby Mode | IVDRIVE | 2.5 | 4 | µA | Standby | 7 | |
| VDRIVE Current, Shutdown Mode | IVDRIVE | 0.5 | 1.5 | µA | Shutdown mode | 7 | |
| Common-Mode Input Range | -10 | 10 | V | ±20 V bipolar differential range | 6 | ||
| Common-Mode Input Range | -7.8 | 7.8 | V | ±12.5 V bipolar differential range | 6 | ||
| Common-Mode Input Range | -6 | 7 | V | ±10 V bipolar differential range | 6 | ||
| Common-Mode Input Range | -3 | 5 | V | ±5 V bipolar differential range | 6 | ||
| Thermal Resistance, junction to ambient (ST-64-2) | θJA | 40 | °C/W | Simulated, JEDEC 2s2p test PCB, natural convection | 11 | ||
| Thermal Resistance, junction to case (ST-64-2) | θJC | 7 | °C/W | 11 |
CAD (KiCad official)
- Symbol:
AD7606C-18BSTZ-RL - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
ad7606c-18bstz-rl-etched.step/ad7606c-18bstz-rl-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7606c-18bstz-rl.step/ad7606c-18bstz-rl.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (75 pp, sha256
8b22bee28f02c95a, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).