AD7606BSTZ-4RL

Analog Devices · ADCs/DACs - Special Purpose · LQFP-64(10x10)

AD7606BSTZ-4RL from Analog Devices, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AVCC	power_in	Analog supply voltage for the front-end amplifiers and ADC core, specified at 4.75 V to 5.25 V and to be decoupled to AGND.
2	AGND	power_in	Analog ground reference for all analog circuitry, to be connected to the system AGND plane.
3	OS0	input	Oversampling mode control input, the LSB of the 3-bit oversampling ratio select (OS[2:0]).
4	OS1	input	Oversampling mode control input, the middle bit of the 3-bit oversampling ratio select (OS[2:0]).
5	OS2	input	Oversampling mode control input, the MSB of the 3-bit oversampling ratio select (OS[2:0]).
6	PAR/SER/BYTE SEL	input	Logic input selecting the parallel interface when low and the serial interface when high; parallel byte mode requires this pin high together with DB15/BYTE SEL high.
7	STBY	input	Standby mode input that powers down most circuitry (except the on-chip reference, regulators and regulator buffers) in standby, or all circuitry in shutdown, with the mode chosen by the RANGE pin state.
8	RANGE	input	Logic input selecting the analog input range for all channels: logic high gives ±10 V and logic low gives ±5 V, with changes taking immediate effect and not recommended during conversion for fast throughput.
9	CONVST A	input	Conversion start input A that initiates simultaneous sampling of V1 and V2 on the AD7606-4 and places their track-and-hold in hold on a low-to-high transition.
10	CONVST B	input	Conversion start input B that initiates simultaneous sampling of V3 and V4 on the AD7606-4 and places their track-and-hold in hold on a low-to-high transition; usable only when oversampling is off.
11	RESET	input	Reset input where a rising edge resets the device, requiring a RESET pulse after power-up, typically 50 ns wide, which aborts a conversion in progress or clears the output registers when applied during a read.
12	RD/SCLK	input	Parallel read control (RD) when the parallel interface is selected, or serial clock input (SCLK) when the serial interface is selected.
13	CS	input	Active-low chip select that frames data transfers; with RD low in parallel mode it enables the DB[15:0] output bus.
14	BUSY	output	Busy output that goes high after the CONVST A and CONVST B rising edges and stays high until all channel conversions complete; its falling edge indicates data is latched and available after time t4.
15	FRSTDATA	output	Digital output that indicates when the V1 result is being read on the parallel, byte or serial interface; it is three-stated when CS is high.
16	DB0	tri_state	Parallel output data bit 0 (LSB) of the conversion result, three-stated when PAR/SER/BYTE SEL is low and tied to AGND when it is high.
17	DB1	tri_state	Parallel output data bit 1 of the conversion result, three-stated when PAR/SER/BYTE SEL is low and tied to AGND when it is high.
18	DB2	tri_state	Parallel output data bit 2 of the conversion result, three-stated when PAR/SER/BYTE SEL is low and tied to AGND when it is high.
19	DB3	tri_state	Parallel output data bit 3 of the conversion result, three-stated when PAR/SER/BYTE SEL is low and tied to AGND when it is high.
20	DB4	tri_state	Parallel output data bit 4 of the conversion result, three-stated when PAR/SER/BYTE SEL is low and tied to AGND when it is high.
21	DB5	tri_state	Parallel output data bit 5 of the conversion result, three-stated when PAR/SER/BYTE SEL is low and tied to AGND when it is high.
22	DB6	tri_state	Parallel output data bit 6 of the conversion result, three-stated when PAR/SER/BYTE SEL is low and tied to AGND when it is high.
23	VDRIVE	power_in	Logic supply input that sets the interface voltage, specified at 2.3 V to 5.25 V and nominally the same supply as the host DSP or FPGA.
24	DB7/DOUTA	tri_state	Parallel output data bit 7 (MSB in byte mode) or serial data output DOUTA when PAR/SER/BYTE SEL is high, three-stated when parallel mode is idle.
25	DB8/DOUTB	tri_state	Parallel output data bit 8 or serial data output DOUTB when PAR/SER/BYTE SEL is high, three-stated when parallel mode is idle.
26	AGND	power_in	Analog ground reference for all analog circuitry, to be connected to the system AGND plane.
27	DB9	tri_state	Parallel output data bit 9 of the conversion result, tied to AGND when PAR/SER/BYTE SEL is high.
28	DB10	tri_state	Parallel output data bit 10 of the conversion result, tied to AGND when PAR/SER/BYTE SEL is high.
29	DB11	tri_state	Parallel output data bit 11 of the conversion result, tied to AGND when PAR/SER/BYTE SEL is high.
30	DB12	tri_state	Parallel output data bit 12 of the conversion result, tied to AGND when PAR/SER/BYTE SEL is high.
31	DB13	tri_state	Parallel output data bit 13 of the conversion result, tied to AGND when PAR/SER/BYTE SEL is high.
32	DB14/HBEN	bidirectional	Parallel output data bit 14, or high byte enable (HBEN) in parallel byte mode selecting MSB-first (HBEN high) or LSB-first (HBEN low) output; tied to GND in serial mode.
33	DB15/BYTE SEL	bidirectional	Parallel output data bit 15, or byte mode select which chooses serial mode (low) or parallel byte mode (high) when PAR/SER/BYTE SEL is high.
34	REF SELECT	input	Internal/external reference selection input where logic high enables the internal 2.5 V reference and logic low disables it, requiring an external 2.5 V reference on REFIN/REFOUT.
35	AGND	power_in	Analog ground reference for all analog circuitry, to be connected to the system AGND plane.
36	REGCAP	power_out	Decoupling pin for the internal regulator output, to be decoupled to AGND with a 1 µF capacitor, with a voltage in the range of 2.5 V to 2.7 V.
37	AVCC	power_in	Analog supply voltage for the front-end amplifiers and ADC core, specified at 4.75 V to 5.25 V and to be decoupled to AGND.
38	AVCC	power_in	Analog supply voltage for the front-end amplifiers and ADC core, specified at 4.75 V to 5.25 V and to be decoupled to AGND.
39	REGCAP	power_out	Decoupling pin for the internal regulator output, to be decoupled to AGND with a 1 µF capacitor, with a voltage in the range of 2.5 V to 2.7 V.
40	AGND	power_in	Analog ground reference for all analog circuitry, to be connected to the system AGND plane.
41	AGND	power_in	Analog ground reference for all analog circuitry, to be connected to the system AGND plane.
42	REFIN/REFOUT	bidirectional	Reference input or output at 2.5 V: it outputs the internal reference when REF SELECT is high, or accepts an external 2.5 V reference when REF SELECT is low, and needs a 10 µF capacitor to ground near REFGND.
43	REFGND	power_in	Reference ground pin that should be connected to AGND.
44	REFCAPA	power_out	Reference buffer output force/sense pin, which must be tied together with REFCAPB and decoupled to AGND with a low ESR 10 µF ceramic capacitor, typically at 4.5 V.
45	REFCAPB	power_out	Reference buffer output force/sense pin, which must be tied together with REFCAPA and decoupled to AGND with a low ESR 10 µF ceramic capacitor, typically at 4.5 V.
46	REFGND	power_in	Reference ground pin that should be connected to AGND.
47	AGND	power_in	Analog ground reference for all analog circuitry, to be connected to the system AGND plane.
48	AVCC	power_in	Analog supply voltage for the front-end amplifiers and ADC core, specified at 4.75 V to 5.25 V and to be decoupled to AGND.
49	V1	passive	Single-ended analog input channel 1 whose input range (±10 V or ±5 V) is set by the RANGE pin.
50	V1GND	power_in	Analog input ground for analog input V1, to be connected to the system AGND plane.
51	V2	passive	Single-ended analog input channel 2 whose input range (±10 V or ±5 V) is set by the RANGE pin.
52	V2GND	power_in	Analog input ground for analog input V2, to be connected to the system AGND plane.
53	AGND	power_in	On the AD7606-4 this pin is an AGND pin (it is an analog input on the 8-channel part), to be connected to the system AGND plane.
54	AGND	power_in	On the AD7606-4 this pin is an AGND pin (it is an analog input ground on the 8-channel part), to be connected to the system AGND plane.
55	AGND	power_in	On the AD7606-4 this pin is an AGND pin (it is an analog input on the 6- and 8-channel parts), to be connected to the system AGND plane.
56	AGND	power_in	On the AD7606-4 this pin is an AGND pin (it is an analog input ground on the 6- and 8-channel parts), to be connected to the system AGND plane.
57	V3	passive	Single-ended analog input channel 3 whose input range (±10 V or ±5 V) is set by the RANGE pin.
58	V3GND	power_in	Analog input ground for analog input V3, to be connected to the system AGND plane.
59	V4	passive	Single-ended analog input channel 4 whose input range (±10 V or ±5 V) is set by the RANGE pin.
60	V4GND	power_in	Analog input ground for analog input V4, to be connected to the system AGND plane.
61	AGND	power_in	On the AD7606-4 this pin is an AGND pin (it is an analog input on the 6- and 8-channel parts), to be connected to the system AGND plane.
62	AGND	power_in	On the AD7606-4 this pin is an AGND pin (it is an analog input ground on the 6- and 8-channel parts), to be connected to the system AGND plane.
63	AGND	power_in	On the AD7606-4 this pin is an AGND pin (it is an analog input on the 8-channel and 6-channel parts), to be connected to the system AGND plane.
64	AGND	power_in	On the AD7606-4 this pin is an AGND pin (it is an analog input ground on the 8-channel and 6-channel parts), to be connected to the system AGND plane.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LQFP-64(10x10)
Category	Data Acquisition
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Signal-to-Noise Ratio (SNR), ±10 V range		94	95.5		dB	Oversampling by 16; ±10 V range; fIN = 130 Hz	4
Signal-to-Noise Ratio (SNR), ±5 V range		93	94.5		dB	Oversampling by 16; ±5 V range; fIN = 130 Hz	4
Signal-to-Noise Ratio (SNR), ±10 V range		88.5	90		dB	No oversampling; ±10 V range	4
Signal-to-Noise Ratio (SNR), ±5 V range		87.5	89		dB	No oversampling; ±5 V range	4
Signal-to-(Noise + Distortion) (SINAD), ±10 V range		88	90		dB	No oversampling; ±10 V range	4
Signal-to-(Noise + Distortion) (SINAD), ±5 V range		87	89		dB	No oversampling; ±5 V range	4
Total Unadjusted Error (TUE), ±10 V range		-6		6	LSB	±10 V range	4
Total Unadjusted Error (TUE), ±5 V range		-12		12	LSB	±5 V range	4
Positive Full-Scale Error Drift		-2		2	ppm/°C	External reference	4
Positive Full-Scale Error Drift		-7		7	ppm/°C	Internal reference	4
Negative Full-Scale Error Drift		-4		4	ppm/°C	External reference	4
Negative Full-Scale Error Drift		-8		8	ppm/°C	Internal reference	4
Reference Input Voltage Range		2.475	2.5	2.525	V	See the ADC Transfer Function section	5
Reference Output Voltage (REFIN/REFOUT)		2.49		2.505	V		5
Reference Temperature Coefficient		-10		10	ppm/°C		5
DC Leakage Current (REFIN/REFOUT)		-1		1	µA		5
Input Current (IIN)	IIN	-2		2	µA	Logic inputs	5
Analog supply voltage (AVCC)	AVCC	4.75		5.25	V		5
Digital I/O supply voltage (VDRIVE)	VDRIVE	2.3		5.25	V		5
Normal Mode (Static) supply current, AD7606-4	ITOTAL		12	17	mA	Digital inputs = 0 V or VDRIVE	5
Normal Mode (Operational) supply current, AD7606-4	ITOTAL		15	21	mA	fSAMPLE = 200 kSPS	5
Standby Mode supply current	ITOTAL		5	8	mA		5
Shutdown Mode supply current	ITOTAL		2	6	µA		5
Power Dissipation Normal Mode (Operational), AD7606-4			75	111	mW	fSAMPLE = 200 kSPS	6
Power Dissipation Standby Mode			25	42	mW		6
Power Dissipation Shutdown Mode			10	31.5	µW		6
AVCC to AGND	AVCC	-0.3		7	V	TA = 25°C	11
Analog Input Voltage to AGND		-16.5		16.5	V		11
Input Current to Any Pin Except Supplies		-10		10	mA		11
Operating Temperature Range (B Version)	TA	-40		85	°C	B version	11
Storage Temperature Range		-65		150	°C		11
Junction Temperature				150	°C		11
Pb/SN Temperature, Soldering Reflow				240	°C	Reflow 10 sec to 30 sec	11
Pb-Free Temperature, Soldering Reflow				260	°C		11
ESD (All Pins Except Analog Inputs)				2	kV		11
ESD (Analog Input Pins Only)				7	kV		11
Junction-to-ambient thermal resistance, 64-lead LQFP	θJA		45		°C/W	4-layer board, device soldered in circuit board	11
Junction-to-case thermal resistance, 64-lead LQFP	θJC		11		°C/W		11

CAD (KiCad official)

Symbol: AD7606BSTZ-4RL
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: ad7606bstz-4rl-etched.step / ad7606bstz-4rl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7606bstz-4rl.step / ad7606bstz-4rl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (36 pp, sha256 fba066bca6916cc7, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# AD7606BSTZ-4RL

**Analog Devices** · ADCs/DACs - Special Purpose · LQFP-64(10x10)

AD7606BSTZ-4RL from Analog Devices, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AVCC | power_in | Analog supply voltage for the front-end amplifiers and ADC core, specified at 4.75 V to 5.25 V and to be decoupled to AGND. |
| 2 | AGND | power_in | Analog ground reference for all analog circuitry, to be connected to the system AGND plane. |
| 3 | OS0 | input | Oversampling mode control input, the LSB of the 3-bit oversampling ratio select (OS[2:0]). |
| 4 | OS1 | input | Oversampling mode control input, the middle bit of the 3-bit oversampling ratio select (OS[2:0]). |
| 5 | OS2 | input | Oversampling mode control input, the MSB of the 3-bit oversampling ratio select (OS[2:0]). |
| 6 | PAR/SER/BYTE SEL | input | Logic input selecting the parallel interface when low and the serial interface when high; parallel byte mode requires this pin high together with DB15/BYTE SEL high. |
| 7 | STBY | input | Standby mode input that powers down most circuitry (except the on-chip reference, regulators and regulator buffers) in standby, or all circuitry in shutdown, with the mode chosen by the RANGE pin state. |
| 8 | RANGE | input | Logic input selecting the analog input range for all channels: logic high gives ±10 V and logic low gives ±5 V, with changes taking immediate effect and not recommended during conversion for fast throughput. |
| 9 | CONVST A | input | Conversion start input A that initiates simultaneous sampling of V1 and V2 on the AD7606-4 and places their track-and-hold in hold on a low-to-high transition. |
| 10 | CONVST B | input | Conversion start input B that initiates simultaneous sampling of V3 and V4 on the AD7606-4 and places their track-and-hold in hold on a low-to-high transition; usable only when oversampling is off. |
| 11 | RESET | input | Reset input where a rising edge resets the device, requiring a RESET pulse after power-up, typically 50 ns wide, which aborts a conversion in progress or clears the output registers when applied during a read. |
| 12 | RD/SCLK | input | Parallel read control (RD) when the parallel interface is selected, or serial clock input (SCLK) when the serial interface is selected. |
| 13 | CS | input | Active-low chip select that frames data transfers; with RD low in parallel mode it enables the DB[15:0] output bus. |
| 14 | BUSY | output | Busy output that goes high after the CONVST A and CONVST B rising edges and stays high until all channel conversions complete; its falling edge indicates data is latched and available after time t4. |
| 15 | FRSTDATA | output | Digital output that indicates when the V1 result is being read on the parallel, byte or serial interface; it is three-stated when CS is high. |
| 16 | DB0 | tri_state | Parallel output data bit 0 (LSB) of the conversion result, three-stated when PAR/SER/BYTE SEL is low and tied to AGND when it is high. |
| 17 | DB1 | tri_state | Parallel output data bit 1 of the conversion result, three-stated when PAR/SER/BYTE SEL is low and tied to AGND when it is high. |
| 18 | DB2 | tri_state | Parallel output data bit 2 of the conversion result, three-stated when PAR/SER/BYTE SEL is low and tied to AGND when it is high. |
| 19 | DB3 | tri_state | Parallel output data bit 3 of the conversion result, three-stated when PAR/SER/BYTE SEL is low and tied to AGND when it is high. |
| 20 | DB4 | tri_state | Parallel output data bit 4 of the conversion result, three-stated when PAR/SER/BYTE SEL is low and tied to AGND when it is high. |
| 21 | DB5 | tri_state | Parallel output data bit 5 of the conversion result, three-stated when PAR/SER/BYTE SEL is low and tied to AGND when it is high. |
| 22 | DB6 | tri_state | Parallel output data bit 6 of the conversion result, three-stated when PAR/SER/BYTE SEL is low and tied to AGND when it is high. |
| 23 | VDRIVE | power_in | Logic supply input that sets the interface voltage, specified at 2.3 V to 5.25 V and nominally the same supply as the host DSP or FPGA. |
| 24 | DB7/DOUTA | tri_state | Parallel output data bit 7 (MSB in byte mode) or serial data output DOUTA when PAR/SER/BYTE SEL is high, three-stated when parallel mode is idle. |
| 25 | DB8/DOUTB | tri_state | Parallel output data bit 8 or serial data output DOUTB when PAR/SER/BYTE SEL is high, three-stated when parallel mode is idle. |
| 26 | AGND | power_in | Analog ground reference for all analog circuitry, to be connected to the system AGND plane. |
| 27 | DB9 | tri_state | Parallel output data bit 9 of the conversion result, tied to AGND when PAR/SER/BYTE SEL is high. |
| 28 | DB10 | tri_state | Parallel output data bit 10 of the conversion result, tied to AGND when PAR/SER/BYTE SEL is high. |
| 29 | DB11 | tri_state | Parallel output data bit 11 of the conversion result, tied to AGND when PAR/SER/BYTE SEL is high. |
| 30 | DB12 | tri_state | Parallel output data bit 12 of the conversion result, tied to AGND when PAR/SER/BYTE SEL is high. |
| 31 | DB13 | tri_state | Parallel output data bit 13 of the conversion result, tied to AGND when PAR/SER/BYTE SEL is high. |
| 32 | DB14/HBEN | bidirectional | Parallel output data bit 14, or high byte enable (HBEN) in parallel byte mode selecting MSB-first (HBEN high) or LSB-first (HBEN low) output; tied to GND in serial mode. |
| 33 | DB15/BYTE SEL | bidirectional | Parallel output data bit 15, or byte mode select which chooses serial mode (low) or parallel byte mode (high) when PAR/SER/BYTE SEL is high. |
| 34 | REF SELECT | input | Internal/external reference selection input where logic high enables the internal 2.5 V reference and logic low disables it, requiring an external 2.5 V reference on REFIN/REFOUT. |
| 35 | AGND | power_in | Analog ground reference for all analog circuitry, to be connected to the system AGND plane. |
| 36 | REGCAP | power_out | Decoupling pin for the internal regulator output, to be decoupled to AGND with a 1 µF capacitor, with a voltage in the range of 2.5 V to 2.7 V. |
| 37 | AVCC | power_in | Analog supply voltage for the front-end amplifiers and ADC core, specified at 4.75 V to 5.25 V and to be decoupled to AGND. |
| 38 | AVCC | power_in | Analog supply voltage for the front-end amplifiers and ADC core, specified at 4.75 V to 5.25 V and to be decoupled to AGND. |
| 39 | REGCAP | power_out | Decoupling pin for the internal regulator output, to be decoupled to AGND with a 1 µF capacitor, with a voltage in the range of 2.5 V to 2.7 V. |
| 40 | AGND | power_in | Analog ground reference for all analog circuitry, to be connected to the system AGND plane. |
| 41 | AGND | power_in | Analog ground reference for all analog circuitry, to be connected to the system AGND plane. |
| 42 | REFIN/REFOUT | bidirectional | Reference input or output at 2.5 V: it outputs the internal reference when REF SELECT is high, or accepts an external 2.5 V reference when REF SELECT is low, and needs a 10 µF capacitor to ground near REFGND. |
| 43 | REFGND | power_in | Reference ground pin that should be connected to AGND. |
| 44 | REFCAPA | power_out | Reference buffer output force/sense pin, which must be tied together with REFCAPB and decoupled to AGND with a low ESR 10 µF ceramic capacitor, typically at 4.5 V. |
| 45 | REFCAPB | power_out | Reference buffer output force/sense pin, which must be tied together with REFCAPA and decoupled to AGND with a low ESR 10 µF ceramic capacitor, typically at 4.5 V. |
| 46 | REFGND | power_in | Reference ground pin that should be connected to AGND. |
| 47 | AGND | power_in | Analog ground reference for all analog circuitry, to be connected to the system AGND plane. |
| 48 | AVCC | power_in | Analog supply voltage for the front-end amplifiers and ADC core, specified at 4.75 V to 5.25 V and to be decoupled to AGND. |
| 49 | V1 | passive | Single-ended analog input channel 1 whose input range (±10 V or ±5 V) is set by the RANGE pin. |
| 50 | V1GND | power_in | Analog input ground for analog input V1, to be connected to the system AGND plane. |
| 51 | V2 | passive | Single-ended analog input channel 2 whose input range (±10 V or ±5 V) is set by the RANGE pin. |
| 52 | V2GND | power_in | Analog input ground for analog input V2, to be connected to the system AGND plane. |
| 53 | AGND | power_in | On the AD7606-4 this pin is an AGND pin (it is an analog input on the 8-channel part), to be connected to the system AGND plane. |
| 54 | AGND | power_in | On the AD7606-4 this pin is an AGND pin (it is an analog input ground on the 8-channel part), to be connected to the system AGND plane. |
| 55 | AGND | power_in | On the AD7606-4 this pin is an AGND pin (it is an analog input on the 6- and 8-channel parts), to be connected to the system AGND plane. |
| 56 | AGND | power_in | On the AD7606-4 this pin is an AGND pin (it is an analog input ground on the 6- and 8-channel parts), to be connected to the system AGND plane. |
| 57 | V3 | passive | Single-ended analog input channel 3 whose input range (±10 V or ±5 V) is set by the RANGE pin. |
| 58 | V3GND | power_in | Analog input ground for analog input V3, to be connected to the system AGND plane. |
| 59 | V4 | passive | Single-ended analog input channel 4 whose input range (±10 V or ±5 V) is set by the RANGE pin. |
| 60 | V4GND | power_in | Analog input ground for analog input V4, to be connected to the system AGND plane. |
| 61 | AGND | power_in | On the AD7606-4 this pin is an AGND pin (it is an analog input on the 6- and 8-channel parts), to be connected to the system AGND plane. |
| 62 | AGND | power_in | On the AD7606-4 this pin is an AGND pin (it is an analog input ground on the 6- and 8-channel parts), to be connected to the system AGND plane. |
| 63 | AGND | power_in | On the AD7606-4 this pin is an AGND pin (it is an analog input on the 8-channel and 6-channel parts), to be connected to the system AGND plane. |
| 64 | AGND | power_in | On the AD7606-4 this pin is an AGND pin (it is an analog input ground on the 8-channel and 6-channel parts), to be connected to the system AGND plane. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LQFP-64(10x10) |
| Category | Data Acquisition |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Signal-to-Noise Ratio (SNR), ±10 V range |  | 94 | 95.5 |  | dB | Oversampling by 16; ±10 V range; fIN = 130 Hz | 4 |
| Signal-to-Noise Ratio (SNR), ±5 V range |  | 93 | 94.5 |  | dB | Oversampling by 16; ±5 V range; fIN = 130 Hz | 4 |
| Signal-to-Noise Ratio (SNR), ±10 V range |  | 88.5 | 90 |  | dB | No oversampling; ±10 V range | 4 |
| Signal-to-Noise Ratio (SNR), ±5 V range |  | 87.5 | 89 |  | dB | No oversampling; ±5 V range | 4 |
| Signal-to-(Noise + Distortion) (SINAD), ±10 V range |  | 88 | 90 |  | dB | No oversampling; ±10 V range | 4 |
| Signal-to-(Noise + Distortion) (SINAD), ±5 V range |  | 87 | 89 |  | dB | No oversampling; ±5 V range | 4 |
| Total Unadjusted Error (TUE), ±10 V range |  | -6 |  | 6 | LSB | ±10 V range | 4 |
| Total Unadjusted Error (TUE), ±5 V range |  | -12 |  | 12 | LSB | ±5 V range | 4 |
| Positive Full-Scale Error Drift |  | -2 |  | 2 | ppm/°C | External reference | 4 |
| Positive Full-Scale Error Drift |  | -7 |  | 7 | ppm/°C | Internal reference | 4 |
| Negative Full-Scale Error Drift |  | -4 |  | 4 | ppm/°C | External reference | 4 |
| Negative Full-Scale Error Drift |  | -8 |  | 8 | ppm/°C | Internal reference | 4 |
| Reference Input Voltage Range |  | 2.475 | 2.5 | 2.525 | V | See the ADC Transfer Function section | 5 |
| Reference Output Voltage (REFIN/REFOUT) |  | 2.49 |  | 2.505 | V |  | 5 |
| Reference Temperature Coefficient |  | -10 |  | 10 | ppm/°C |  | 5 |
| DC Leakage Current (REFIN/REFOUT) |  | -1 |  | 1 | µA |  | 5 |
| Input Current (IIN) | IIN | -2 |  | 2 | µA | Logic inputs | 5 |
| Analog supply voltage (AVCC) | AVCC | 4.75 |  | 5.25 | V |  | 5 |
| Digital I/O supply voltage (VDRIVE) | VDRIVE | 2.3 |  | 5.25 | V |  | 5 |
| Normal Mode (Static) supply current, AD7606-4 | ITOTAL |  | 12 | 17 | mA | Digital inputs = 0 V or VDRIVE | 5 |
| Normal Mode (Operational) supply current, AD7606-4 | ITOTAL |  | 15 | 21 | mA | fSAMPLE = 200 kSPS | 5 |
| Standby Mode supply current | ITOTAL |  | 5 | 8 | mA |  | 5 |
| Shutdown Mode supply current | ITOTAL |  | 2 | 6 | µA |  | 5 |
| Power Dissipation Normal Mode (Operational), AD7606-4 |  |  | 75 | 111 | mW | fSAMPLE = 200 kSPS | 6 |
| Power Dissipation Standby Mode |  |  | 25 | 42 | mW |  | 6 |
| Power Dissipation Shutdown Mode |  |  | 10 | 31.5 | µW |  | 6 |
| AVCC to AGND | AVCC | -0.3 |  | 7 | V | TA = 25°C | 11 |
| Analog Input Voltage to AGND |  | -16.5 |  | 16.5 | V |  | 11 |
| Input Current to Any Pin Except Supplies |  | -10 |  | 10 | mA |  | 11 |
| Operating Temperature Range (B Version) | TA | -40 |  | 85 | °C | B version | 11 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 11 |
| Junction Temperature |  |  |  | 150 | °C |  | 11 |
| Pb/SN Temperature, Soldering Reflow |  |  |  | 240 | °C | Reflow 10 sec to 30 sec | 11 |
| Pb-Free Temperature, Soldering Reflow |  |  |  | 260 | °C |  | 11 |
| ESD (All Pins Except Analog Inputs) |  |  |  | 2 | kV |  | 11 |
| ESD (Analog Input Pins Only) |  |  |  | 7 | kV |  | 11 |
| Junction-to-ambient thermal resistance, 64-lead LQFP | θJA |  | 45 |  | °C/W | 4-layer board, device soldered in circuit board | 11 |
| Junction-to-case thermal resistance, 64-lead LQFP | θJC |  | 11 |  | °C/W |  | 11 |

## CAD (KiCad official)

- Symbol: `AD7606BSTZ-4RL`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `ad7606bstz-4rl-etched.step` / `ad7606bstz-4rl-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7606bstz-4rl.step` / `ad7606bstz-4rl.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586181906232168448) (36 pp, sha256 `fba066bca6916cc7`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad7606bstz-4rl-datasheet.pdf)