component
AD7524JRZ-REEL7
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DACs), SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAD7524JRZ-REEL7
Analog Devices · Digital To Analog Converters (DACs) · SOP-16
AD7524JRZ-REEL7 from Analog Devices, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT1 | output | DAC current output 1, with output capacitance of 120 pF max when all digital inputs are high and 30 pF max when low, rated -0.3 V to VDD+0.3 V. |
| 2 | OUT2 | output | DAC current output 2, with output capacitance of 30 pF max when all digital inputs are high and 120 pF max when low, rated -0.3 V to VDD+0.3 V. |
| 3 | GND | power_in | Ground reference for the supply, digital inputs and analog outputs. |
| 4 | DB7 (MSB) | input | Digital data bit 7 (most significant bit), TTL/CMOS compatible input with range -0.3 V to VDD+0.3 V. |
| 5 | DB6 | input | Digital data bit 6 input, TTL/CMOS compatible with range -0.3 V to VDD+0.3 V. |
| 6 | DB5 | input | Digital data bit 5 input, TTL/CMOS compatible with range -0.3 V to VDD+0.3 V. |
| 7 | DB4 | input | Digital data bit 4 input, TTL/CMOS compatible with range -0.3 V to VDD+0.3 V. |
| 8 | DB3 | input | Digital data bit 3 input, TTL/CMOS compatible with range -0.3 V to VDD+0.3 V. |
| 9 | DB2 | input | Digital data bit 2 input, TTL/CMOS compatible with range -0.3 V to VDD+0.3 V. |
| 10 | DB1 | input | Digital data bit 1 input, TTL/CMOS compatible with range -0.3 V to VDD+0.3 V. |
| 11 | DB0 (LSB) | input | Digital data bit 0 (least significant bit) input, TTL/CMOS compatible with range -0.3 V to VDD+0.3 V. |
| 12 | CS | input | Active-low chip select; with WR low the DAC is in write mode, and when high the device is in hold mode. |
| 13 | WR | input | Active-low write input; with CS low the DAC responds to the data bus, and when high the device holds the last data. |
| 14 | VDD | power_in | Positive supply, operating from +5 V to +15 V with an absolute maximum of +17 V. |
| 15 | VREF | power_in | Reference voltage input, rated ±25 V, with input resistance of 5 kΩ min to 20 kΩ max to GND. |
| 16 | RFEEDBACK | passive | Internal feedback resistor terminal for the external output amplifier, rated ±25 V to GND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOP-16 |
| Category | Data Converters |
| Pins | 16 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Relative Accuracy (J version), TA = +25°C | -0.5 | 0.5 | LSB | VDD = +15 V, TA = +25°C | 2 | ||
| Relative Accuracy (J version), TMIN to TMAX | -0.5 | 0.5 | LSB | VDD = +15 V, TMIN to TMAX | 2 | ||
| Gain Error, TMIN to TMAX | -1.5 | 1.5 | LSB | VDD = +15 V, TMIN to TMAX; gain error measured using internal feedback resistor | 2 | ||
| Average Gain TC, TA = +25°C | -10 | 10 | ppm/°C | VDD = +15 V, TA = +25°C; gain TC measured from +25°C to TMIN or from +25°C to TMAX | 2 | ||
| Average Gain TC, TMIN to TMAX | -10 | 10 | ppm/°C | VDD = +15 V, TMIN to TMAX; gain TC measured from +25°C to TMIN or from +25°C to TMAX | 2 | ||
| DC Supply Rejection, TA = +25°C | ∆Gain/∆VDD | 0.02 | % FSR/% | ∆VDD = ±10%; VDD = +15 V, TA = +25°C | 2 | ||
| DC Supply Rejection, TMIN to TMAX | ∆Gain/∆VDD | 0.04 | % FSR/% | ∆VDD = ±10%; VDD = +15 V, TMIN to TMAX | 2 | ||
| Output Leakage Current IOUT1 (Pin 1), TA = +25°C | IOUT1 | -50 | 50 | nA | DB0-DB7 = 0 V; WR, CS = 0 V; VREF = ±10 V; VDD = +15 V, TA = +25°C | 2 | |
| Output Leakage Current IOUT1 (Pin 1), TMIN to TMAX | IOUT1 | -200 | 200 | nA | DB0-DB7 = 0 V; WR, CS = 0 V; VREF = ±10 V; VDD = +15 V, TMIN to TMAX | 2 | |
| Output Leakage Current IOUT2 (Pin 2), TA = +25°C | IOUT2 | -50 | 50 | nA | DB0-DB7 = VDD; WR, CS = 0 V; VREF = ±10 V; VDD = +15 V, TA = +25°C | 2 | |
| Output Leakage Current IOUT2 (Pin 2), TMIN to TMAX | IOUT2 | -200 | 200 | nA | DB0-DB7 = VDD; WR, CS = 0 V; VREF = ±10 V; VDD = +15 V, TMIN to TMAX | 2 | |
| Output Current Settling Time (to 1/2 LSB), TA = +25°C | 250 | ns | OUT1 Load = 100 Ω, CEXT = 13 pF; WR, CS = 0 V; DB0-DB7 = 0 V to VDD to 0 V; VDD = +15 V, TA = +25°C | 2 | |||
| Output Current Settling Time (to 1/2 LSB), TMIN to TMAX | 350 | ns | OUT1 Load = 100 Ω, CEXT = 13 pF; WR, CS = 0 V; DB0-DB7 = 0 V to VDD to 0 V; VDD = +15 V, TMIN to TMAX | 2 | |||
| AC Feedthrough at OUT1, TA = +25°C | 0.25 | % FSR | VREF = ±10 V, 100 kHz Sine Wave; DB0-DB7 = 0 V; WR, CS = 0 V; VDD = +15 V, TA = +25°C | 2 | |||
| AC Feedthrough at OUT1, TMIN to TMAX | 0.5 | % FSR | VREF = ±10 V, 100 kHz Sine Wave; DB0-DB7 = 0 V; WR, CS = 0 V; VDD = +15 V, TMIN to TMAX | 2 | |||
| AC Feedthrough at OUT2, TA = +25°C | 0.25 | % FSR | VREF = ±10 V, 100 kHz Sine Wave; DB0-DB7 = 0 V; WR, CS = 0 V; VDD = +15 V, TA = +25°C | 2 | |||
| AC Feedthrough at OUT2, TMIN to TMAX | 0.5 | % FSR | VREF = ±10 V, 100 kHz Sine Wave; DB0-DB7 = 0 V; WR, CS = 0 V; VDD = +15 V, TMIN to TMAX | 2 | |||
| Output Capacitance COUT1 (Pin 1) | COUT1 | 120 | pF | DB0-DB7 = VDD; WR, CS = 0 V | 2 | ||
| Output Capacitance COUT2 (Pin 2) | COUT2 | 30 | pF | 2 | |||
| Output Capacitance COUT1 (Pin 1) | COUT1 | 30 | pF | DB0-DB7 = 0 V; WR, CS = 0 V | 2 | ||
| Output Capacitance COUT2 (Pin 2) | COUT2 | 120 | pF | 2 | |||
| Reference Input Resistance RIN (Pin 15 to GND), minimum | RIN | 5 | kΩ | Pin 15 to GND | 2 | ||
| Reference Input Resistance RIN (Pin 15 to GND), maximum | RIN | 20 | kΩ | Pin 15 to GND | 2 | ||
| DAC thin-film resistor temperature coefficient (RIN) | -300 | ppm/°C | Approximately; footnote 4, Pin 15 to GND | 2 | |||
| Input Capacitance DB0-DB7 | 5 | pF | VIN = 0 V | 2 | |||
| Input Capacitance WR, CS | 20 | pF | VIN = 0 V | 2 | |||
| Input HIGH Voltage VIH, TA = +25°C | VIH | 13.5 | V | VDD = +15 V, TA = +25°C | 2 | ||
| Input HIGH Voltage VIH, TMIN to TMAX | VIH | 13.5 | V | VDD = +15 V, TMIN to TMAX | 2 | ||
| Input LOW Voltage VIL, TA = +25°C | VIL | 1.5 | V | VDD = +15 V, TA = +25°C | 2 | ||
| Input LOW Voltage VIL, TMIN to TMAX | VIL | 1.5 | V | VDD = +15 V, TMIN to TMAX | 2 | ||
| Input Current IIN, TA = +25°C | IIN | -1 | 1 | µA | VIN = 0 V or VDD; VDD = +15 V, TA = +25°C | 2 | |
| Input Current IIN, TMIN to TMAX | IIN | -10 | 10 | µA | VIN = 0 V or VDD; VDD = +15 V, TMIN to TMAX | 2 | |
| Chip Select to Write Setup Time tCS (AD7524J), TA = +25°C | tCS | 100 | ns | AD7524J; tWR = tCS; VDD = +15 V, TA = +25°C; see timing diagram | 2 | ||
| Chip Select to Write Setup Time tCS (AD7524J), TMIN to TMAX | tCS | 130 | ns | AD7524J; tWR = tCS; VDD = +15 V, TMIN to TMAX; see timing diagram | 2 | ||
| Write Pulse Width tWR (AD7524J), TA = +25°C | tWR | 100 | ns | AD7524J; tCS ≥ tWR, tCH ≥ 0; VDD = +15 V, TA = +25°C | 2 | ||
| Write Pulse Width tWR (AD7524J), TMIN to TMAX | tWR | 130 | ns | AD7524J; tCS ≥ tWR, tCH ≥ 0; VDD = +15 V, TMIN to TMAX | 2 | ||
| Data Setup Time tDS (AD7524J), TA = +25°C | tDS | 60 | ns | AD7524J; VDD = +15 V, TA = +25°C | 2 | ||
| Data Setup Time tDS (AD7524J), TMIN to TMAX | tDS | 80 | ns | AD7524J; VDD = +15 V, TMIN to TMAX | 2 | ||
| Chip Select to Write Hold Time tCH | tCH | 0 | ns | All grades | 2 | ||
| Data Hold Time tDH | tDH | 10 | ns | All grades | 2 | ||
| Supply Current IDD, TA = +25°C | IDD | 2 | mA | All digital inputs VIL or VIH; VDD = +15 V, TA = +25°C | 2 | ||
| Supply Current IDD, TMIN to TMAX | IDD | 2 | mA | All digital inputs VIL or VIH; VDD = +15 V, TMIN to TMAX | 2 | ||
| Supply Current IDD (static), TA = +25°C | IDD | 100 | µA | All digital inputs 0 V or VDD; VDD = +15 V, TA = +25°C | 2 | ||
| Supply Current IDD (static), TMIN to TMAX | IDD | 500 | µA | All digital inputs 0 V or VDD; VDD = +15 V, TMIN to TMAX | 2 | ||
| VDD to GND | VDD | -0.3 | 17 | V | TA = +25°C, unless otherwise noted | 3 | |
| VRFB to GND | VRFB | -25 | 25 | V | TA = +25°C, unless otherwise noted | 3 | |
| VREF to GND | VREF | -25 | 25 | V | TA = +25°C, unless otherwise noted | 3 | |
| Digital Input Voltage to GND (upper limit VDD + 0.3 V) | -0.3 | V | TA = +25°C, unless otherwise noted | 3 | |||
| OUT1, OUT2 to GND (upper limit VDD + 0.3 V) | -0.3 | V | TA = +25°C, unless otherwise noted | 3 | |||
| Power Dissipation (Any Package), to +75°C | 450 | mW | To +75°C; derates above 75°C by 6 mW/°C | 3 | |||
| Operating Temperature, Commercial (J, K, L) | -40 | 85 | °C | 3 | |||
| Storage Temperature | -65 | 150 | °C | 3 | |||
| Lead Temperature (Soldering, 10 secs) | 300 | °C | Soldering, 10 secs | 3 |
CAD (KiCad official)
- Symbol:
AD7524JRZ-REEL7 - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SOP-16 (KiCad packages3D, STEP)
- 3D model files:
ad7524jrz-reel7-etched.step/ad7524jrz-reel7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7524jrz-reel7.step/ad7524jrz-reel7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (8 pp, sha256
ad65e6a97c1dd82b, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).