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AD7495ARMZ

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Analog Devices Analog To Digital Converters (ADCs), MSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD7495ARMZ

Analog Devices · Analog To Digital Converters (ADCs) · MSOP-8

AD7495ARMZ from Analog Devices, in a MSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 REF OUT power_out Reference output for the AD7495 requires a minimum 100 nF capacitance to GND, and buffering is required before the internal reference is applied elsewhere in the system.
2 VIN power_in Single-ended analog input channel with an input range of 0 to REF IN.
3 GND power_in Analog ground reference point for all circuitry; all analog input signals and any external reference signal are referred to this voltage.
4 SCLK input Serial clock logic input that provides the serial clock for accessing data and is also the clock source for the conversion process.
5 SDATA output Serial data output carrying four leading zeros followed by the 12 conversion bits MSB first, clocked out on the falling edge of SCLK.
6 VDRIVE power_in Logic power supply input that sets the operating voltage of the serial interface.
7 CS input Active-low chip select logic input that initiates conversions and frames the serial data transfer.
8 VDD power_in Power supply input with a VDD range of 2.7 V to 5.25 V.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package MSOP-8
Category Data Converters
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Signal-to-Noise and Distortion Ratio (SINAD) 68 dB fIN = 300 kHz sine wave, fSAMPLE = 1 MSPS 5
Total Harmonic Distortion (THD) -75 dB fIN = 300 kHz sine wave, fSAMPLE = 1 MSPS 5
Peak Harmonic or Spurious Noise (SFDR) -76 dB fIN = 300 kHz sine wave, fSAMPLE = 1 MSPS 5
Integral Nonlinearity -1.5 1.5 LSB @ 5 V 5
Differential Nonlinearity -0.9 1.5 LSB @ 5 V guaranteed no missed codes to 12 bits 5
Offset Error -8 8 LSB 5
Gain Error -7 7 LSB 5
DC Leakage Current (analog input) -1 1 µA 5
REF OUT Output Voltage 2.4625 2.5375 V 5
Input Low Voltage VINL 0.4 V 5
Input Current IIN -1 1 µA Typically 10 nA, VIN = 0 V or VDRIVE 5
Input Capacitance, CIN CIN 10 pF 5
Output Low Voltage VOL 0.4 V ISINK = 200 µA 5
Floating-State Leakage Current -10 10 µA 5
Floating-State Output Capacitance 10 pF 5
Conversion Time 800 ns 16 SCLK cycles with SCLK @ 20 MHz 5
Track-and-Hold Acquisition Time 300 ns Sine wave input 5
Track-and-Hold Acquisition Time 325 ns Full-scale step input 5
Throughput Rate 1 MSPS See the Serial Interface section 5
VDD VDD 2.7 5.25 V 6
VDRIVE VDRIVE 2.7 5.25 V 6
Normal Mode (Operational) IDD 2.6 mA VDD = 4.75 V to 5.25 V, fSAMPLE = 1 MSPS 6
Normal Mode (Operational) IDD 2 mA VDD = 2.7 V to 3.6 V, fSAMPLE = 1 MSPS 6
Partial Power-Down Mode (Static) IDD 230 µA Static 6
Full Power-Down Mode IDD 1 µA Static, SCLK on or off 6
Power Dissipation, Normal Mode (Operational) 13 mW VDD = 5 V, fSAMPLE = 1 MSPS 6
Power Dissipation, Normal Mode (Operational) 6 mW VDD = 3 V, fSAMPLE = 1 MSPS 6
Power Dissipation, Partial Power-Down (Static) 1.15 mW VDD = 5 V 6
Power Dissipation, Partial Power-Down (Static) 690 µW VDD = 3 V 6
Power Dissipation, Full Power-Down 5 µW VDD = 5 V 6
Power Dissipation, Full Power-Down 3 µW VDD = 3 V 6
SCLK Frequency (lower limit) fSCLK 10 kHz 7
SCLK Frequency (upper limit) fSCLK 20 MHz 7
Minimum Quiet Time between conversions tQUIET 100 ns 7
CS to SCLK setup time t2 10 ns 7
Delay from CS until SDATA three-state disabled t3 22 ns 7
Data access time after SCLK falling edge t4 40 ns 7
SCLK low pulse width t5 0.4 tSCLK 7
SCLK high pulse width t6 0.4 tSCLK 7
SCLK to data valid hold time t7 10 ns 7
SCLK falling edge to SDATA high impedance (minimum) t8 10 ns 7
SCLK falling edge to SDATA high impedance (maximum) t8 45 ns 7
CS rising edge to SDATA high impedance t9 20 ns 7
Power-up time from full power-down (AD7495) tPOWER-UP 650 µs 7
VDD to GND VDD -0.3 7 V 9
Digital Input Voltage to GND -0.3 7 V 9
Input Current to Any Pin Except Supplies -10 10 mA Transient currents up to 100 mA do not cause SCR latch-up 9
Operating Temperature Range (Commercial A, B Version) TA -40 85 °C 9
Storage Temperature Range -65 150 °C 9
Junction Temperature 150 °C 9
SOIC, MSOP Package Power Dissipation 450 mW 9
θJA Thermal Impedance (MSOP) θJA 205.9 °C/W 9
θJC Thermal Impedance (MSOP) θJC 43.74 °C/W 9

CAD (KiCad official)

  • Symbol: AD7495ARMZ
  • Footprint: Package_SO:MSOP-8_3x3mm_P0.65mm
  • 3D model: MSOP-8 (KiCad packages3D, STEP)
  • 3D model files: ad7495armz-etched.step / ad7495armz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7495armz.step / ad7495armz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (24 pp, sha256 b85f8429dbca0035, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF