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AD7477AAKSZ-500RL7
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADCs), SC-70-6. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD7477AAKSZ-500RL7
Analog Devices · Analog To Digital Converters (ADCs) · SC-70-6
AD7477AAKSZ-500RL7 from Analog Devices, in a SC-70-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Power supply input with a VDD range of 2.35 V to 5.25 V, which also sets the 0 V to VDD analog input range. |
| 2 | GND | power_in | Analog ground, the reference point for all circuitry on the part, to which all analog input signals should be referred. |
| 3 | VIN | power_in | Single-ended analog input channel with an input range of 0 V to VDD. |
| 4 | SCLK | input | Serial clock logic input that clocks data out of the part and also serves as the clock source for the conversion process. |
| 5 | SDATA | output | Logic output providing the conversion result as a serial data stream, MSB first, clocked out on the falling edge of SCLK, with four leading zeros followed by the conversion data (the AD7477A sends 10 bits followed by two trailing zeros). |
| 6 | CS | input | Active-low chip select logic input that initiates conversions and frames the serial data transfer. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SC-70-6 |
| Category | Data Converters |
| Pins | 6 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD to GND | VDD | -0.3 | 7 | V | 10 | ||
| Digital Input Voltage to GND | -0.3 | 7 | V | 10 | |||
| Analog Input Voltage to GND | VIN | -0.3 | V | Upper limit printed as VDD + 0.3 V | 10 | ||
| Digital Output Voltage to GND | -0.3 | V | Upper limit printed as VDD + 0.3 V | 10 | |||
| Input Current to Any Pin Except Supplies | 10 | mA | 10 | ||||
| Operating Temperature Range (Commercial, A and B Grades) | -40 | 85 | °C | Commercial (A and B grades) | 10 | ||
| Storage Temperature Range | -65 | 150 | °C | 10 | |||
| Junction Temperature | 150 | °C | 10 | ||||
| ESD | 3.5 | kV | All other models (not AD7476AWYRMZ, AD7476AWYRMZ-RL7) | 10 | |||
| Minimum SCLK Frequency | fSCLK | 10 | kHz | A, B grades; minimum fSCLK at which specifications are guaranteed | 8 | ||
| Maximum SCLK Frequency | fSCLK | 20 | MHz | 8 | |||
| CS Pulse Width | t1 | 10 | ns | Minimum CS pulse width | 8 | ||
| CS to SCLK Setup Time | t2 | 10 | ns | CS to SCLK setup time | 8 | ||
| Delay from CS until SDATA Three-State Disabled | t3 | 22 | ns | Measured with load circuit Figure 2 | 8 | ||
| Data Access Time after SCLK Falling Edge | t4 | 40 | ns | Measured with load circuit Figure 2 | 8 | ||
| SCLK Low Pulse Width | t5 | 0.4 | tSCLK | 8 | |||
| SCLK High Pulse Width | t6 | 0.4 | tSCLK | 8 | |||
| SCLK to Data Valid Hold Time | t7 | 10 | ns | VDD ≤ 3.3 V | 8 | ||
| SCLK to Data Valid Hold Time | t7 | 9.5 | ns | 3.3 V < VDD ≤ 3.6 V | 8 | ||
| SCLK to Data Valid Hold Time | t7 | 7 | ns | VDD > 3.6 V | 8 | ||
| SCLK Falling Edge to SDATA High Impedance | t8 | 36 | ns | Measured with load circuit Figure 2 | 8 | ||
| Minimum Quiet Time between Bus Relinquish and Start of Next Conversion | tQUIET | 50 | ns | 8 | |||
| Power-Up Time from Full Power-Down | tPOWER-UP | 1 | µs | 8 | |||
| Conversion Time (AD7477A) | tCONVERT | 14 | × tSCLK | AD7477A: 14 × tSCLK | 8 | ||
| SC70 Thermal Impedance, Junction-to-Ambient | θJA | 340.2 | °C/W | SC70 package | 10 | ||
| SC70 Thermal Impedance, Junction-to-Case | θJC | 228.9 | °C/W | SC70 package | 10 |
CAD (KiCad official)
- Symbol:
AD7477AAKSZ-500RL7 - Footprint:
Package_TO_SOT_SMD:SOT-363_SC-70-6 - 3D model: SC-70-6 (KiCad packages3D, STEP)
- 3D model files:
ad7477aaksz-500rl7-etched.step/ad7477aaksz-500rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7477aaksz-500rl7.step/ad7477aaksz-500rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (28 pp, sha256
f7084789e08c0a5a, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD7477AAKSZ-500RL7
**Analog Devices** · Analog To Digital Converters (ADCs) · SC-70-6
AD7477AAKSZ-500RL7 from Analog Devices, in a SC-70-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Power supply input with a VDD range of 2.35 V to 5.25 V, which also sets the 0 V to VDD analog input range. |
| 2 | GND | power_in | Analog ground, the reference point for all circuitry on the part, to which all analog input signals should be referred. |
| 3 | VIN | power_in | Single-ended analog input channel with an input range of 0 V to VDD. |
| 4 | SCLK | input | Serial clock logic input that clocks data out of the part and also serves as the clock source for the conversion process. |
| 5 | SDATA | output | Logic output providing the conversion result as a serial data stream, MSB first, clocked out on the falling edge of SCLK, with four leading zeros followed by the conversion data (the AD7477A sends 10 bits followed by two trailing zeros). |
| 6 | CS | input | Active-low chip select logic input that initiates conversions and frames the serial data transfer. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SC-70-6 |
| Category | Data Converters |
| Pins | 6 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD to GND | VDD | -0.3 | | 7 | V | | 10 |
| Digital Input Voltage to GND | | -0.3 | | 7 | V | | 10 |
| Analog Input Voltage to GND | VIN | -0.3 | | | V | Upper limit printed as VDD + 0.3 V | 10 |
| Digital Output Voltage to GND | | -0.3 | | | V | Upper limit printed as VDD + 0.3 V | 10 |
| Input Current to Any Pin Except Supplies | | | | 10 | mA | | 10 |
| Operating Temperature Range (Commercial, A and B Grades) | | -40 | | 85 | °C | Commercial (A and B grades) | 10 |
| Storage Temperature Range | | -65 | | 150 | °C | | 10 |
| Junction Temperature | | | | 150 | °C | | 10 |
| ESD | | | | 3.5 | kV | All other models (not AD7476AWYRMZ, AD7476AWYRMZ-RL7) | 10 |
| Minimum SCLK Frequency | fSCLK | 10 | | | kHz | A, B grades; minimum fSCLK at which specifications are guaranteed | 8 |
| Maximum SCLK Frequency | fSCLK | | | 20 | MHz | | 8 |
| CS Pulse Width | t1 | 10 | | | ns | Minimum CS pulse width | 8 |
| CS to SCLK Setup Time | t2 | 10 | | | ns | CS to SCLK setup time | 8 |
| Delay from CS until SDATA Three-State Disabled | t3 | | | 22 | ns | Measured with load circuit Figure 2 | 8 |
| Data Access Time after SCLK Falling Edge | t4 | | | 40 | ns | Measured with load circuit Figure 2 | 8 |
| SCLK Low Pulse Width | t5 | 0.4 | | | tSCLK | | 8 |
| SCLK High Pulse Width | t6 | 0.4 | | | tSCLK | | 8 |
| SCLK to Data Valid Hold Time | t7 | 10 | | | ns | VDD ≤ 3.3 V | 8 |
| SCLK to Data Valid Hold Time | t7 | 9.5 | | | ns | 3.3 V < VDD ≤ 3.6 V | 8 |
| SCLK to Data Valid Hold Time | t7 | 7 | | | ns | VDD > 3.6 V | 8 |
| SCLK Falling Edge to SDATA High Impedance | t8 | | | 36 | ns | Measured with load circuit Figure 2 | 8 |
| Minimum Quiet Time between Bus Relinquish and Start of Next Conversion | tQUIET | 50 | | | ns | | 8 |
| Power-Up Time from Full Power-Down | tPOWER-UP | | | 1 | µs | | 8 |
| Conversion Time (AD7477A) | tCONVERT | | 14 | | × tSCLK | AD7477A: 14 × tSCLK | 8 |
| SC70 Thermal Impedance, Junction-to-Ambient | θJA | | 340.2 | | °C/W | SC70 package | 10 |
| SC70 Thermal Impedance, Junction-to-Case | θJC | | 228.9 | | °C/W | SC70 package | 10 |
## CAD (KiCad official)
- Symbol: `AD7477AAKSZ-500RL7`
- Footprint: `Package_TO_SOT_SMD:SOT-363_SC-70-6`
- 3D model: SC-70-6 (KiCad packages3D, STEP)
- 3D model files: `ad7477aaksz-500rl7-etched.step` / `ad7477aaksz-500rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7477aaksz-500rl7.step` / `ad7477aaksz-500rl7.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7476A_7477A_7478A.pdf) (28 pp, sha256 `f7084789e08c0a5a`, retrieved 2026-10-28, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad7477aaksz-500rl7-datasheet.pdf)