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AD74412RBCPZ

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Analog Devices Analog To Digital Converters (ADCs), LFCSP-64(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentdata convertersad74412rbcpzfactory-2.0.0extractor-text

Verified AD74412RBCPZ

by Ray · last 31 Oct 2026 · 1 record · files match
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Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 65 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD74412RBCPZ · LFCSP-64(9x9) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 66-page datasheet
  • ✓distributor: lcsc C648855, digikey 505-AD74412RBCPZ-ND, mouser 584-AD74412RBCPZ
  • ✓family: QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-qpjb2mj3/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.66)
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad74412rbcpz.kicad_sym✓ ad74412rbcpz.kicad_mod✓ ad74412rbcpz.step
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Ray Publish 0.1.0 931660f 2d ago

AD74412RBCPZ

Analog Devices · Analog To Digital Converters (ADCs) · LFCSP-64(9x9)

AD74412RBCPZ from Analog Devices, in a LFCSP-64(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SENSEH_A input High-side sense pin on channel A that closes the loop in current output mode, routed to the AD74412R side of RSENSE.
2 SENSEHF_A input Filtered high-side sense pin on channel A that can be switched to the ADC inputs, routed to the AD74412R side of RSENSE through the off-chip filter.
3 SENSEL_A input Low-side sense pin on channel A that closes the loop in voltage and current output modes, routed to the I/OP_x screw terminal side of RSENSE.
4 SENSELF_A input Filtered low-side sense pin on channel A that can be switched to the ADC inputs, routed to the I/OP_x screw terminal side of RSENSE through the off-chip filter.
5 VIOUTP_A bidirectional Voltage or current high-side force pin on channel A, working with VIOUTN_A to provide a voltage or current to the I/OP_x screw terminal.
6 VIOUTN_A bidirectional Voltage or current low-side force pin on channel A, working with VIOUTP_A to provide a voltage or current to the I/OP_x screw terminal.
7 AVDD power_in Positive analog supply, 14 V to 26.4 V.
8 AGND1 power_in Analog ground.
9 ALDO5V power_out 5 V analog LDO output; decouple with the recommended capacitor in Table 27 and do not use externally.
10 ALDO1V8 power_out 1.8 V analog LDO output; decouple with the recommended capacitor in Table 27 and do not use externally.
11 VIOUTN_B bidirectional Voltage or current low-side force pin on channel B, working with VIOUTP_B to provide a voltage or current to the I/OP_x screw terminal.
12 VIOUTP_B bidirectional Voltage or current high-side force pin on channel B, working with VIOUTN_B to provide a voltage or current to the I/OP_x screw terminal.
13 SENSELF_B input Filtered low-side sense pin on channel B that can be switched to the ADC inputs, routed to the I/OP_x screw terminal side of RSENSE through the off-chip filter.
14 SENSEL_B input Low-side sense pin on channel B that closes the loop in voltage and current output modes, routed to the I/OP_x screw terminal side of RSENSE.
15 SENSEHF_B input Filtered high-side sense pin on channel B that can be switched to the ADC inputs, routed to the AD74412R side of RSENSE through the off-chip filter.
16 SENSEH_B input High-side sense pin on channel B that closes the loop in current output mode, routed to the AD74412R side of RSENSE.
17 CASCODE_B output Gate drive pin for the optional external power-dissipating FET on channel B; leave disconnected if the FET is not used.
18 CCOMP_B passive Compensation capacitor pin for channel B allowing high capacitive loads in voltage output; connect the capacitor to the AD74412R side of RSENSE.
19 GPO_A output General-purpose digital output A that can monitor the digital input comparator output.
20 GPO_B output General-purpose digital output B that can monitor the digital input comparator output.
21 GPO_C output General-purpose digital output C that can monitor the digital input comparator output.
22 GPO_D output General-purpose digital output D that can monitor the digital input comparator output.
23 DVCC power_in Digital supply, 2.7 V to 5.5 V; decouple with the recommended capacitor in Table 27.
24 CPUMP_P passive Charge pump fly capacitor terminal; connect the recommended fly capacitor between CPUMP_P and CPUMP_N.
25 DGND power_in Digital ground.
26 CPUMP_N passive Charge pump fly capacitor terminal; connect the recommended fly capacitor between CPUMP_P and CPUMP_N.
27 AVSS power_out Charge pump output voltage equal to negative DVCC; do not use externally.
28 AGND3 power_in Analog ground.
29 REFIN input 2.5 V reference input.
30 REFOUT output Internal 2.5 V reference output; must be connected to REFIN to use the internal reference.
31 CCOMP_C passive Compensation capacitor pin for channel C allowing high capacitive loads in voltage output; connect the capacitor to the AD74412R side of RSENSE.
32 CASCODE_C output Gate drive pin for the optional external power-dissipating FET on channel C; leave disconnected if the FET is not used.
33 SENSEH_C input High-side sense pin on channel C that closes the loop in current output mode, routed to the AD74412R side of RSENSE.
34 SENSEHF_C input Filtered high-side sense pin on channel C that can be switched to the ADC inputs, routed to the AD74412R side of RSENSE through the off-chip filter.
35 SENSEL_C input Low-side sense pin on channel C that closes the loop in voltage and current output modes, routed to the I/OP_x screw terminal side of RSENSE.
36 SENSELF_C input Filtered low-side sense pin on channel C that can be switched to the ADC inputs, routed to the I/OP_x screw terminal side of RSENSE through the off-chip filter.
37 VIOUTP_C bidirectional Voltage or current high-side force pin on channel C, working with VIOUTN_C to provide a voltage or current to the I/OP_x screw terminal.
38 VIOUTN_C bidirectional Voltage or current low-side force pin on channel C, working with VIOUTP_C to provide a voltage or current to the I/OP_x screw terminal.
39 RESERVED passive Reserved pin; tie to ground.
40 AGND2 power_in Analog ground.
41 AGND_SENSE input Analog ground sense; tie this pin to the I/ON_x screw terminal.
42 AVDD power_in Positive analog supply, 14 V to 26.4 V.
43 VIOUTN_D bidirectional Voltage or current low-side force pin on channel D, working with VIOUTP_D to provide a voltage or current to the I/OP_x screw terminal.
44 VIOUTP_D bidirectional Voltage or current high-side force pin on channel D, working with VIOUTN_D to provide a voltage or current to the I/OP_x screw terminal.
45 SENSELF_D input Filtered low-side sense pin on channel D that can be switched to the ADC inputs, routed to the I/OP_x screw terminal side of RSENSE through the off-chip filter.
46 SENSEL_D input Low-side sense pin on channel D that closes the loop in voltage and current output modes, routed to the I/OP_x screw terminal side of RSENSE.
47 SENSEHF_D input Filtered high-side sense pin on channel D that can be switched to the ADC inputs, routed to the AD74412R side of RSENSE through the off-chip filter.
48 SENSEH_D input High-side sense pin on channel D that closes the loop in current output mode, routed from the AD74412R side of RSENSE.
49 CASCODE_D output Gate drive pin for the optional external power-dissipating FET on channel D; leave disconnected if the FET is not used.
50 CCOMP_D passive Compensation capacitor pin for channel D allowing high capacitive loads in voltage output; connect the capacitor to the AD74412R side of RSENSE.
51 SDO tri_state Serial interface data out.
52 ADC_RDY output Active-low open-drain output that asserts when a new sequence of ADC conversion results is ready; connect to a pull-up resistor to IOVDD.
53 ALERT output Active-low open-drain output that asserts low on an alert condition (read the ALERT_STATUS register); connect to IOVDD via a pull-up resistor.
54 DGND power_in Digital ground.
55 IOVDD power_in Input/output supply, 1.7 V to 5.5 V.
56 DVCC power_in Digital supply, 2.7 V to 5.5 V.
57 DLDO1V8 power_out 1.8 V digital LDO output; decouple with the recommended capacitor in Table 27 and do not use externally.
58 LDAC input Active-low load DAC input that updates all four DACs in parallel; can be tied permanently low if simultaneous updates are not required.
59 SCLK input Serial interface clock.
60 SDI input Serial interface data in.
61 SYNC input Active-low serial interface frame synchronization input.
62 RESET input Active-low hardware reset input that resets the AD74412R to the power-on state.
63 CCOMP_A passive Compensation capacitor pin for channel A allowing high capacitive loads in voltage output; connect the capacitor to the AD74412R side of RSENSE.
64 CASCODE_A output Gate drive pin for the optional external power-dissipating FET on channel A; leave disconnected if the FET is not used.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-64(9x9)
Category Data Converters
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Total Unadjusted Error (voltage output) TUE -0.4 0.4 %FSR Internal reference 5
Total Unadjusted Error (voltage output) TUE -0.35 0.35 %FSR External reference 5
TUE at 25°C (voltage output) TUE -0.2 0.2 %FSR Internal reference 5
TUE at 25°C (voltage output) TUE 0.15 %FSR External reference 5
Integral Nonlinearity (voltage output) INL -4 4 LSB 5
Differential Nonlinearity (voltage output) DNL -1 1 LSB Guaranteed monotonic 5
Offset Error (voltage output) -8 8 mV 5
Gain Error (voltage output) -0.4 0.4 %FSR Internal reference 5
Gain Error (voltage output) -0.25 0.25 %FSR External reference 5
Short-Circuit Current (Sourcing) 25 29 32 mA Per channel, lower limit bit = 0 (default) 5
Short-Circuit Current (Sourcing) 5.5 7 9 mA Per channel, lower limit bit = 1 5
Short-Circuit Current (Sinking) 3 3.8 4.5 mA 5
Voltage Output Range 0 11 V 5
TUE (current output) TUE -0.55 0.55 %FSR Internal reference 6
TUE (current output) TUE -0.45 0.45 %FSR External reference 6
TUE at 25°C (current output) TUE -0.35 0.35 %FSR Internal reference 6
TUE at 25°C (current output) TUE -0.2 0.2 %FSR External reference 6
INL (current output) INL -4 4 LSB From zero-scale to full-scale 6
DNL (current output) DNL -1 1 LSB Guaranteed monotonic 6
Offset Error (current output) -37.5 5 37.5 µA 6
Gain Error (current output) -0.4 0.4 %FSR Internal reference 6
Gain Error (current output) -0.3 0.3 %FSR External reference 6
Output Impedance (current output) 1.5 4 MΩ 6
TUE (voltage input) TUE -0.4 0.4 %FSR Internal reference 7
TUE (voltage input) TUE -0.2 0.2 %FSR External reference 7
TUE at 25°C (voltage input) TUE -0.3 0.3 %FSR Internal reference 7
TUE at 25°C (voltage input) TUE -0.1 0.1 %FSR External reference 7
INL (voltage input) INL -5 2 5 LSB 7
Input Bias Current at 25°C -100 100 nA 200 kΩ to GND is disabled (CH_200K_TO_GND bit = 0), does not include TVS leakage 7
Input Resistance 175 195 215 kΩ 200 kΩ to GND enabled 7
Reference Input Voltage 2.495 2.5 2.505 V 12
Reference Input DC Input Current -1 1 µA 12
Reference Output Voltage 2.495 2.5 2.505 V TA = 25°C 12
Reference Temperature Coefficient 20 ppm/°C 12
Logic Input Current -1 1 µA Per pin 13
SDO Output Low Voltage VOL 0.4 V Sink current (ISINK) = 200 µA 13
Supply Voltage AVDD AVDD 14 24 26.4 V 13
Supply Voltage DVCC DVCC 2.7 3.3 5.5 V 13
Supply Voltage IOVDD IOVDD 1.7 5.5 V 13
AVDD Current 10 13.5 18 mA AD74412R powered up and in high-Z mode 13
AVDD Current 10 12.5 14 mA Four channels configured in any output mode, no load current 13
AVDD Current 10 15 18.5 mA Four channels configured in any input mode, no load current 13
DVCC Current 5.5 9 13.5 mA AD74412R powered up and in high-Z mode 14
DVCC Current 8.5 10.5 12.5 mA Four channels configured in any output mode, no load current 14
SCLK pin cycle time t1 42 ns IOVDD = 2.7 V to 5.5V 14
SYNC high time t6 650 ns 14
SCLK rising edge to SDO valid t10 23 ns IOVDD = 2.7 V to 5.5V 14
AVDD to AGND -0.3 30 V TA = 25°C 16
REFIN, REFOUT to AGND -0.3 5 V TA = 25°C 16
DVCC, IOVDD to DGND -0.3 6 V TA = 25°C 16
Operating Temperature Range -40 85 °C 16
Storage Temperature Range -65 150 °C 16
Junction Temperature TJ 125 °C 16

CAD (KiCad official)

  • Symbol: AD74412RBCPZ
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: LFCSP-64(9x9) (KiCad packages3D, STEP)
  • 3D model files: ad74412rbcpz-etched.step / ad74412rbcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad74412rbcpz.step / ad74412rbcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (66 pp, sha256 c9e95c6c8e5d2c0a, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF