component
AD7398BRUZ
Public Made by Adomby adom
Analog Devices Digital To Analog Converters (DACs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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"component": {
"mpn": "AD7398BRUZ",
"manufacturer": "Analog Devices",
"package": "TSSOP-16",
"pin_count": 16,
"category": "ADC/DAC/Data Conversion",
"subcategory": "Digital To Analog Converters (DACs)",
"datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD7398_7399.pdf",
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"distributor_links": {
"lcsc": "C578429",
"digikey": "505-AD7398BRUZ-ND",
"mouser": "584-AD7398BRUZ"
},
"distributor_check": {
"checked_at": "2026-10-30T20:16:00Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "505-AD7398BRUZ-ND",
"status": "found"
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"mouser": {
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"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "VOUTB",
"type": "output",
"description": "DAC B voltage output, which swings over 0 to VREF."
},
{
"number": "2",
"name": "VOUTA",
"type": "output",
"description": "DAC A voltage output, which swings over 0 to VREF."
},
{
"number": "3",
"name": "VSS",
"type": "power_in",
"description": "Negative power supply input with a specified operating range of 0 V to −5.5 V."
},
{
"number": "4",
"name": "VREFA",
"type": "input",
"description": "DAC A reference voltage input that sets the DAC A full-scale output and may be tied to VDD or VSS."
},
{
"number": "5",
"name": "VREFB",
"type": "input",
"description": "DAC B reference voltage input that sets the DAC B full-scale output and may be tied to VDD or VSS."
},
{
"number": "6",
"name": "GND",
"type": "power_in",
"description": "Ground pin."
},
{
"number": "7",
"name": "LDAC",
"type": "input",
"description": "Level-sensitive active-low asynchronous load-DAC strobe that transfers all input register data to the DAC registers."
},
{
"number": "8",
"name": "RS",
"type": "input",
"description": "Active-low asynchronous reset that forces the input and DAC registers to all-zero codes without changing the shift register contents."
},
{
"number": "9",
"name": "CS",
"type": "input",
"description": "Active-low chip select that disables shift-register loading when high and transfers serial register data to the input register on its rising edge."
},
{
"number": "10",
"name": "CLK",
"type": "input",
"description": "Schmitt-triggered clock input where the positive edge clocks data into the shift register."
},
{
"number": "11",
"name": "SDI",
"type": "input",
"description": "Serial data input that loads directly into the shift register."
},
{
"number": "12",
"name": "VREFD",
"type": "input",
"description": "DAC D reference voltage input that sets the DAC D full-scale output and may be tied to VDD or VSS."
},
{
"number": "13",
"name": "VREFC",
"type": "input",
"description": "DAC C reference voltage input that sets the DAC C full-scale output and may be tied to VDD or VSS."
},
{
"number": "14",
"name": "VDD",
"type": "power_in",
"description": "Positive power supply input with a specified operating range of 3 V to 5 V ±10%."
},
{
"number": "15",
"name": "VOUTD",
"type": "output",
"description": "DAC D voltage output, which swings over 0 to VREF."
},
{
"number": "16",
"name": "VOUTC",
"type": "output",
"description": "DAC C voltage output, which swings over 0 to VREF."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The datasheet gives pin functions but not KiCad ERC classes; analog outputs were typed as output and"
],
"pages_sent": 7,
"cost_usd": 0.0444,
"at": "2026-10-30T20:15:33"
},
"datasheet": {
"url": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD7398_7399.pdf",
"pages": 24,
"sha256": "161ffba861d9601a",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 16,
"described": 16,
"cites_pages": true,
"refuses_to_fabricate": true
}
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"up": "Z",
"units": "mm",
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"seat": "z = 0",
"extents_mm": [
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"checked": "2026-10-30",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
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"package_dims": {
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"source_page": 20,
"D": {
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"E1": {
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}