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AD7398BRUZ

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Analog Devices Digital To Analog Converters (DACs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad7398bruzfactory-2.0.0extractor-text

Verified AD7398BRUZ

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 16 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD7398BRUZ · TSSOP-16 · 16 pins
  • ✓copper: 16 copper pads, none touching another net
  • ✓datasheet: all 16 pin names found in the 24-page datasheet
  • ✓distributor: lcsc C578429, digikey 505-AD7398BRUZ-ND, mouser 584-AD7398BRUZ
  • ✓family: TSSOP-16_4.4x5mm_P0.65mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-q2bu2ogl/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.20)
  • ✓pads: 16 pins = 16 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 16 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad7398bruz.kicad_sym✓ ad7398bruz.kicad_mod✓ ad7398bruz.step
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AD7398BRUZ

Analog Devices · Digital To Analog Converters (DACs) · TSSOP-16

AD7398BRUZ from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUTB output DAC B voltage output, which swings over 0 to VREF.
2 VOUTA output DAC A voltage output, which swings over 0 to VREF.
3 VSS power_in Negative power supply input with a specified operating range of 0 V to −5.5 V.
4 VREFA input DAC A reference voltage input that sets the DAC A full-scale output and may be tied to VDD or VSS.
5 VREFB input DAC B reference voltage input that sets the DAC B full-scale output and may be tied to VDD or VSS.
6 GND power_in Ground pin.
7 LDAC input Level-sensitive active-low asynchronous load-DAC strobe that transfers all input register data to the DAC registers.
8 RS input Active-low asynchronous reset that forces the input and DAC registers to all-zero codes without changing the shift register contents.
9 CS input Active-low chip select that disables shift-register loading when high and transfers serial register data to the input register on its rising edge.
10 CLK input Schmitt-triggered clock input where the positive edge clocks data into the shift register.
11 SDI input Serial data input that loads directly into the shift register.
12 VREFD input DAC D reference voltage input that sets the DAC D full-scale output and may be tied to VDD or VSS.
13 VREFC input DAC C reference voltage input that sets the DAC C full-scale output and may be tied to VDD or VSS.
14 VDD power_in Positive power supply input with a specified operating range of 3 V to 5 V ±10%.
15 VOUTD output DAC D voltage output, which swings over 0 to VREF.
16 VOUTC output DAC C voltage output, which swings over 0 to VREF.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-16
Category ADC/DAC/Data Conversion
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Relative Accuracy (INL) INL -1.5 1.5 LSB 3
Differential Nonlinearity (DNL) DNL -1 1 LSB Monotonic 3
Zero-Scale Error VZSE -2.5 2.5 mV Data = 000H 3
Full-Scale Voltage Error VFSE -2.5 2.5 mV Data = FFFH 3
Capacitive Load CL 200 pF 3 V to 5 V ±10% column; No oscillation 3
Capacitive Load CL 400 pF ±5 V ±10% column; No oscillation 3
Logic Input Low Voltage VIL 0.5 V VDD = 3 V 3
Logic Input Low Voltage VIL 0.8 V VDD = 5 V 3
Logic Input High Voltage VIH 80 % VDD CLK only; 3 V to 5 V ±10% column 3
Logic Input High Voltage VIH 4 V CLK only; ±5 V ±10% column 3
Logic Input High Voltage VIH 2.1 V Other inputs; 3 V to 5 V ±10% column; printed as 2.1 to 2.4 V min 3
Logic Input High Voltage VIH 2.4 V Other inputs; ±5 V ±10% column 3
Input Leakage Current IIL 1 μA 3
Input Capacitance CIL 10 pF 3
Clock Frequency fCLK 11 MHz 3 V to 5 V ±10% column 3
Clock Frequency fCLK 16.6 MHz ±5 V ±10% column 3
Clock Width High tCH 45 ns 3 V to 5 V ±10% column 3
Clock Width High tCH 30 ns ±5 V ±10% column 3
Clock Width Low tCL 45 ns 3 V to 5 V ±10% column 3
Clock Width Low tCL 30 ns ±5 V ±10% column 3
CS to Clock Setup tCSS 10 ns 3 V to 5 V ±10% column 3
CS to Clock Setup tCSS 5 ns ±5 V ±10% column 3
Clock to CS Hold tCSH 20 ns 3 V to 5 V ±10% column 3
Clock to CS Hold tCSH 15 ns ±5 V ±10% column 3
Load DAC Pulse Width tLDAC 45 ns 3 V to 5 V ±10% column 3
Load DAC Pulse Width tLDAC 30 ns ±5 V ±10% column 3
Data Setup tDS 15 ns 3 V to 5 V ±10% column 3
Data Setup tDS 10 ns ±5 V ±10% column 3
Data Hold tDH 10 ns 3 V to 5 V ±10% column 3
Data Hold tDH 5 ns ±5 V ±10% column 3
Load Setup to CS tLDS 0 ns 3
Load Hold to CS tLDH 20 ns 3 V to 5 V ±10% column 3
Load Hold to CS tLDH 15 ns ±5 V ±10% column 3
Shutdown Supply Current IDD_SD 30 60 μA No load 4
Positive Supply Current IDD 1.5 2.8 mA VIL = 0 V, no load, −40°C < TA < +125°C; 3 V to 5 V ±10% column 4
Positive Supply Current IDD 1.6 3 mA VIL = 0 V, no load, −40°C < TA < +125°C; ±5 V ±10% column 4
Positive Supply Current IDD 1.5 2.6 mA VIL = 0 V, no load, −40°C < TA < +85°C; 3 V to 5 V ±10% column 4
Positive Supply Current IDD 1.6 2.8 mA VIL = 0 V, no load, −40°C < TA < +85°C; ±5 V ±10% column 4
Negative Supply Current ISS 1.5 2.5 mA VIL = 0 V, no load; 3 V to 5 V ±10% column 4
Negative Supply Current ISS 1.6 2.7 mA VIL = 0 V, no load; ±5 V ±10% column 4
Power Supply Sensitivity PSS 0.006 %/% ΔVDD = ±5% 4
Maximum VDD to GND VDD -0.3 7 V VDD to GND 6
Maximum VSS to GND VSS -7 0.3 V VSS to GND 6
Logic Inputs to GND -0.3 8 V Logic inputs to GND 6
IOUT Short Circuit to GND IOUT 50 mA Short circuit to GND 6
Maximum Junction Temperature TJ Max 150 °C 6
Storage Temperature Range -65 150 °C 6
Reflow Soldering Peak Temperature 260 °C Pb-free 6
Thermal Resistance (θJA) θJA 180 °C/W 16-Lead TSSOP Package (RU-16) 6
Operating Temperature Range TA -40 125 °C 6
Positive Power Supply Input VDD 3 5 V Specified range 3 V to 5 V ±10% (pin 14) 7
Negative Power Supply Input VSS -5.5 0 V Specified range of operation 0 V to −5.5 V (pin 3) 7

CAD (KiCad official)

  • Symbol: AD7398BRUZ
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: ad7398bruz-etched.step / ad7398bruz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7398bruz.step / ad7398bruz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (24 pp, sha256 161ffba861d9601a, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF