component
AD7380BCPZ-RL7
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADCs), LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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AD7380BCPZ-RL7
Analog Devices · Analog To Digital Converters (ADCs) · LFCSP-16(3x3)
AD7380BCPZ-RL7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground reference point for all circuitry on the device. |
| 2 | VLOGIC | power_in | Logic interface supply voltage, 1.65 V to 3.6 V, decoupled to GND with a 1 μF capacitor. |
| 3 | REGCAP | passive | Decoupling pin for the internal regulator output (1.9 V typical), decoupled to GND with a 1 μF capacitor. |
| 4 | VCC | power_in | Power supply input voltage, 3.0 V to 3.6 V, decoupled to GND with a 1 μF capacitor. |
| 5 | AINB− | input | Negative analog input of ADC B, forming a differential pair with AINB+. |
| 6 | AINB+ | input | Positive analog input of ADC B, forming a differential pair with AINB−. |
| 7 | AINA− | input | Negative analog input of ADC A, forming a differential pair with AINA+. |
| 8 | AINA+ | input | Positive analog input of ADC A, forming a differential pair with AINA−. |
| 9 | REFCAP | passive | Decoupling pin for the band gap reference (2.5 V typical), decoupled to GND with a 0.1 μF capacitor. |
| 10 | GND | power_in | Ground reference point for all circuitry on the device. |
| 11 | REFIO | bidirectional | Reference input/output: outputs the on-chip 2.5 V reference or accepts an external 2.5 V to 3.3 V reference, requiring a 1 μF capacitor to GND. |
| 12 | CS | input | Active-low chip select input that initiates conversions and frames the serial data transfer. |
| 13 | SDOA | output | Serial data output A for ADC A or ADC B conversion results or on-chip register data. |
| 14 | SDOB/ALERT | output | Serial data output B for ADC B results, or active-low alert output indicating a conversion result exceeded a configured threshold. |
| 15 | SDI | input | Serial data input providing the data written to the on-chip control registers. |
| 16 | SCLK | input | Serial clock input for data transfers to and from the ADC. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-16(3x3) |
| Category | ADC/DAC/Data Conversion |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Differential Nonlinearity Error | DNL | -1 | 0.7 | 1 | LSB | 3 | |
| Integral Nonlinearity Error | INL | -2 | 0.75 | 2 | LSB | 3 | |
| Gain Error | -0.015 | 0.002 | 0.015 | % FS | 3 | ||
| Gain Error Temperature Drift | -11 | 1 | 11 | ppm/°C | 3 | ||
| Gain Error Match | -0.01 | 0.002 | 0.01 | % FS | 3 | ||
| Zero Error | -0.2 | 0.01 | 0.2 | mV | At 25°C, VCC = 3.3 V | 3 | |
| Zero Error (full temperature) | -0.5 | 0.5 | mV | 3 | |||
| Zero Error Drift | -2 | 0.5 | 2 | μV/°C | 3 | ||
| Zero Error Matching | -0.5 | 0.1 | 0.5 | mV | 3 | ||
| No Missing Codes | 16 | Bits | 3 | ||||
| Signal-to-Noise Ratio | SNR | 90 | 92.5 | dB | VREF = 3.3 V external, fIN = 1 kHz | 3 | |
| Signal-to-Noise Ratio | SNR | 88.5 | 91.1 | dB | 3 | ||
| Signal-to-(Noise + Distortion) | SINAD | 89.5 | 92.3 | dB | VREF = 3.3 V external | 3 | |
| Signal-to-(Noise + Distortion) | SINAD | 88 | 91 | dB | 3 | ||
| VCC Current Normal Mode (Operational) | IVCC | 21.5 | 26 | mA | 3 | ||
| Total Power | PTOTAL | 83 | 107 | mW | 3 | ||
| VCC Power Normal Mode (Operational) | PVCC | 71 | 94 | mW | 3 | ||
| DC Leakage Current | 0.1 | 1 | μA | 5 | |||
| Aperture Delay Match | 26 | 100 | ps | 5 | |||
| VREF Input Voltage Range | VREF | 2.49 | 3.4 | V | External reference | 5 | |
| VREF Input Current | 0.47 | 0.51 | mA | External reference | 5 | ||
| VREF Output Voltage | VREF | 2.498 | 2.5 | 2.502 | V | At 25°C | 5 |
| VREF Output Voltage | VREF | 2.495 | 2.505 | V | −40°C to +125°C | 5 | |
| VREF Temperature Coefficient | 1 | 10 | ppm/°C | 5 | |||
| Input Low Current | IIL | -1 | 1 | μA | 5 | ||
| Input High Current | IIH | -1 | 1 | μA | 5 | ||
| Output Low Voltage | VOL | 0.4 | V | Sink current (ISINK) = +300 μA | 5 | ||
| Floating State Leakage Current | -1 | 1 | μA | 5 | |||
| Supply Voltage | VCC | 3 | 3.3 | 3.6 | V | 5 | |
| Supply Voltage, external reference 3.3 V | VCC | 3.2 | 3.3 | 3.6 | V | External reference = 3.3 V | 5 |
| Logic Supply Voltage | VLOGIC | 1.65 | 3.6 | V | 5 | ||
| IVCC Normal Mode (Static) | IVCC | 2.3 | 2.8 | mA | 5 | ||
| IVCC Shutdown Mode | IVCC | 100 | 200 | μA | 5 | ||
| IVLOGIC Normal Mode (Static) | IVLOGIC | 10 | 200 | nA | SDOA and SDOB at 0x1FFF | 5 | |
| IVLOGIC Normal Mode (Operational) | IVLOGIC | 3.5 | 3.7 | mA | SDOA and SDOB at 0x1FFF | 5 | |
| IVLOGIC Shutdown Mode | IVLOGIC | 10 | 200 | nA | SDOA and SDOB at 0x1FFF | 5 | |
| PVCC Normal Mode (Static) | PVCC | 7.6 | 10 | mW | 6 | ||
| PVCC Shutdown Mode | PVCC | 330 | 720 | μW | 6 | ||
| PVLOGIC Normal Mode (Operational) | PVLOGIC | 11.5 | 13.3 | mW | SDOA and SDOB at 0x1FFF | 6 | |
| Time between conversions | tCYC | 250 | ns | 6 | |||
| SCLK period | tSCLK | 12.5 | ns | 6 | |||
| VCC to GND | -0.3 | 4 | V | 8 | |||
| VLOGIC to GND | -0.3 | 4 | V | 8 | |||
| Input Current to Any Pin Except Supplies | -10 | 10 | mA | 8 | |||
| Operating Temperature Range | -40 | 125 | °C | 8 | |||
| Storage Temperature Range | -65 | 150 | °C | 8 | |||
| Junction Temperature | 150 | °C | 8 | ||||
| Pb-Free Soldering Reflow Temperature | 260 | °C | 8 | ||||
| ESD HBM | 4 | kV | 8 | ||||
| ESD FICDM | 1.25 | kV | 8 | ||||
| Thermal Resistance Junction to Ambient | θJA | 55.4 | °C/W | CP-16-45, JEDEC 2S2P board, four thermal vias | 8 | ||
| Thermal Resistance Junction to Case | θJC | 12.7 | °C/W | CP-16-45, JEDEC 2S2P board, four thermal vias | 8 |
CAD (KiCad official)
- Symbol:
AD7380BCPZ-RL7 - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
ad7380bcpz-rl7-etched.step/ad7380bcpz-rl7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7380bcpz-rl7.step/ad7380bcpz-rl7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (31 pp, sha256
ae40a540b706f2c6, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).