# AD736JNZ

**Analog Devices** · RMS-to-DC Converters · PDIP-8

AD736JNZ from Analog Devices, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CC | input | Coupling capacitor pin: connect a coupling capacitor here for dc coupling at Pin 2, or connect to ground if Pin 2 is ac coupled; also a low impedance input with 8 kΩ input impedance for high input voltages and low supply voltages. |
| 2 | VIN | power_in | High input impedance (10^12 Ω) signal input pin. |
| 3 | CF | passive | Connect an auxiliary low-pass filter capacitor from the output. |
| 4 | -VS | power_in | Negative supply voltage if dual supplies are used, or ground if connected to a single-supply source. |
| 5 | CAV | passive | Connect the averaging capacitor here. |
| 6 | OUTPUT | output | Buffered DC output voltage. |
| 7 | +VS | power_in | Positive supply voltage. |
| 8 | COM | passive | Common. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | PDIP-8 |
| Category | ADC/DAC/Data Conversion |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Total Error, Internal Trim, 0 to 200 mV rms (mV part) |  |  | 0.3 | 0.5 | ±mV | 1 kHz sine wave, 0 mV rms to 200 mV rms, using CC | 3 |
| Total Error, Internal Trim, 0 to 200 mV rms (% of reading part) |  |  | 0.3 | 0.5 | ±% of reading | 1 kHz sine wave, 0 mV rms to 200 mV rms, using CC | 3 |
| Total Error, 200 mV to 1 V rms |  |  | -1.2 | 2 | % of reading | 1 kHz sine wave, 200 mV to 1 V rms | 3 |
| Temperature drift of total error, J grade |  |  | 0.007 |  | ±% of reading/°C | TMIN to TMAX, J and K grades @ 200 mV rms | 3 |
| Error vs supply voltage (±5 V to ±16.5 V) |  | 0 | 0.06 | 0.1 | %/V | @ 200 mV rms input, VS = ±5 V to ±16.5 V | 3 |
| Error vs supply voltage (±5 V to ±3 V) |  | 0 | -0.18 | -0.3 | %/V | @ 200 mV rms input, VS = ±5 V to ±3 V | 3 |
| DC Reversal Error |  |  | 1.3 | 2.5 | % of reading | DC-coupled @ 600 mV dc | 3 |
| Nonlinearity |  | 0 | 0.25 | 0.35 | % of reading | 0 mV to 200 mV @ 100 mV rms | 3 |
| Total Error, External Trim (mV part) |  |  |  | 0.1 | ±mV | 0 mV rms to 200 mV rms | 3 |
| Total Error, External Trim (% part) |  |  |  | 0.5 | ±% of reading | 0 mV rms to 200 mV rms | 3 |
| Additional error, crest factor 1 to 3 |  |  | 0.7 |  | % additional error | CAV, CF = 100 µF | 3 |
| Additional error, crest factor 3 to 5 |  |  | 2.5 |  | % additional error | CAV, CF = 100 µF | 3 |
| High-Z Input Bias Current |  |  | 1 | 25 | pA | VS = ±3 V to ±16.5 V | 3 |
| Low-Z Input Resistance |  | 6.4 | 8 | 9.6 | kΩ | Pin 1 | 3 |
| Input Offset Voltage, J grade |  | -3 |  | 3 | mV | J and K Grades | 3 |
| Input offset vs temperature |  |  | 8 | 30 | µV/°C |  | 3 |
| Input offset vs supply (±5 V to ±16.5 V) |  |  | 50 | 150 | µV/V | VS = ±5 V to ±16.5 V | 3 |
| Input offset vs supply (±5 V to ±3 V) |  |  | 80 |  | µV/V | VS = ±5 V to ±3 V | 3 |
| Maximum continuous nondestructive input |  |  | 12 |  | V p-p | All supply voltages (printed ±12) | 3 |
| Output Offset Voltage, J grade |  |  | 0.1 | 0.5 | mV | J and K Grades (printed ±) | 4 |
| Output offset vs temperature |  |  | 1 | 20 | µV/°C |  | 4 |
| Output offset vs supply (±5 V to ±16.5 V) |  |  | 50 | 130 | µV/V | VS = ±5 V to ±16.5 V | 4 |
| Output offset vs supply (±5 V to ±3 V) |  |  | 50 |  | µV/V | VS = ±5 V to ±3 V | 4 |
| Output Voltage Swing, 2 kΩ load |  |  | 1.7 |  | V | VS = +2.8 V, −3.2 V; 0 to 1.6 min | 4 |
| Output Voltage Swing, 2 kΩ load |  |  | 3.8 |  | V | VS = ±5 V; 0 to 3.6 min | 4 |
| Output Voltage Swing, 2 kΩ load |  | 4 | 5 |  | V | VS = ±16.5 V | 4 |
| Output Voltage Swing, no load |  | 4 | 12 |  | V | VS = ±16.5 V | 4 |
| Output Current |  |  | 2 |  | mA |  | 4 |
| Short-Circuit Current |  |  | 3 |  | mA |  | 4 |
| Output Resistance |  |  | 0.2 |  | Ω | @ dc | 4 |
| Operating Voltage Range | VS |  | 5 | 16.5 | V | Printed +2.8, −3.2 min; ±5 typ; ±16.5 max | 4 |
| Quiescent Current, zero signal | IQ |  | 160 | 200 | µA | Zero signal | 4 |
| Quiescent Current, 200 mV rms | IQ |  | 230 | 270 | µA | 200 mV rms, No Load, sine wave input | 4 |
| Operating temperature, commercial |  | 0 |  | 70 | °C | AD736JN | 4 |
| Supply Voltage |  | -16.5 |  | 16.5 | V | ±16.5 V | 5 |
| Internal Power Dissipation |  |  |  | 200 | mW |  | 5 |
| Input Voltage Pin 1 |  | -12 |  | 12 | V | Pin 1 | 5 |
| Storage Temperature Range (N) |  | -65 |  | 125 | °C | N, R | 5 |
| Lead Temperature |  |  |  | 300 | °C | Soldering, 60 sec | 5 |
| ESD Rating |  |  |  | 500 | V |  | 5 |
| Thermal Resistance 8-Lead PDIP | θJA |  | 165 |  | °C/W | 8-Lead PDIP | 5 |

## CAD (KiCad official)

- Symbol: `AD736JNZ`
- Footprint: `Package_DIP:DIP-8_W7.62mm`
- 3D model: PDIP-8 (KiCad packages3D, STEP)
- 3D model files: `ad736jnz-etched.step` / `ad736jnz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad736jnz.step` / `ad736jnz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD736.pdf) (20 pp, sha256 `356adc34359eea11`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ad736jnz-datasheet.pdf)