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AD7367BRUZ
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Analog Devices Analog To Digital Converters (ADCs), TSSOP-24. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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AD7367BRUZ
Analog Devices · Analog To Digital Converters (ADCs) · TSSOP-24
AD7367BRUZ from Analog Devices, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DOUTA | output | Serial data output for ADC A, clocked out on the falling edge of SCLK, with 14 SCLK cycles required to read a 14-bit AD7367 result MSB first. |
| 2 | VDRIVE | power_in | Logic power supply input with a range of 2.7 V to 5.25 V that must never exceed DVCC or AVCC by more than 0.3 V, and must be at least 4.75 V to reach 1 MSPS for the AD7367. |
| 3 | DVCC | power_in | Digital supply voltage of 4.75 V to 5.25 V that should be shorted to AVCC and decoupled to DGND with 10 µF and 100 nF capacitors. |
| 4 | RANGE1 | input | Logic input for analog input range selection that sets the input range together with RANGE0 per Table 8. |
| 5 | RANGE0 | input | Logic input for analog input range selection that sets the input range together with RANGE1 per Table 8. |
| 6 | ADDR | input | Multiplexer select logic input that chooses Channel 1 or Channel 2 of both ADCs, latched on the rising edge of BUSY. |
| 7 | AGND | power_in | Analog ground reference for all analog circuitry, which must not be more than 0.3 V from DGND even on a transient basis. |
| 8 | AVCC | power_in | Analog supply for the ADC cores with a range of 4.75 V to 5.25 V, decoupled to AGND with 10 µF and 100 nF capacitors. |
| 9 | DCAPA | passive | Reference buffer decoupling pin for ADC A that takes a 680 nF capacitor and can be driven by an external 3 V reference when REFSEL is low. |
| 10 | VSS | power_in | Negative high-voltage analog supply that must be less than −11.5 V for all analog input ranges and be decoupled with 10 µF and 100 nF capacitors. |
| 11 | VA1 | input | Single-ended analog input channel 1 of ADC A whose range is set by RANGE0 and RANGE1. |
| 12 | VA2 | input | Single-ended analog input channel 2 of ADC A whose range is set by RANGE0 and RANGE1. |
| 13 | VB2 | input | Single-ended analog input channel 2 of ADC B whose range is set by RANGE0 and RANGE1. |
| 14 | VB1 | input | Single-ended analog input channel 1 of ADC B whose range is set by RANGE0 and RANGE1. |
| 15 | VDD | power_in | Positive high-voltage analog supply that must be greater than 11.5 V for all analog input ranges and be decoupled with 10 µF and 100 nF capacitors. |
| 16 | DCAPB | passive | Reference buffer decoupling pin for ADC B that takes a 680 nF capacitor and can accept an external 3 V reference when REFSEL is low. |
| 17 | AGND | power_in | Second analog ground pin that must connect to the system AGND plane and stay within 0.3 V of DGND. |
| 18 | REFSEL | input | Logic input that selects the on-chip 2.5 V reference when tied high or an external reference via DCAPA/DCAPB when tied to GND. |
| 19 | CS | input | Active-low chip select that frames the serial transfer and enables the DOUTA and DOUTB outputs when low. |
| 20 | SCLK | input | Serial clock logic input that clocks out conversion data from the device. |
| 21 | CNVST | input | Edge-triggered conversion start input whose falling edge starts a conversion and whose low level at end of conversion puts the part into power-down. |
| 22 | BUSY | output | Busy output that goes high when a conversion starts and stays high until the conversion completes. |
| 23 | DOUTB | output | Serial data output for ADC B, clocked out on the falling edge of SCLK, which also carries the second ADC result when CS is held low for a further 14 SCLK cycles. |
| 24 | DGND | power_in | Digital ground reference for all digital circuitry that must be within 0.3 V of AGND even on a transient basis. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-24 |
| Category | Data Converters |
| Pins | 24 |
CAD (KiCad official)
- Symbol:
AD7367BRUZ - Footprint:
Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm - 3D model: TSSOP-24 (KiCad packages3D, STEP)
- 3D model files:
ad7367bruz-etched.step/ad7367bruz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7367bruz.step/ad7367bruz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (28 pp, sha256
73011d26fda7310e, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# AD7367BRUZ
**Analog Devices** · Analog To Digital Converters (ADCs) · TSSOP-24
AD7367BRUZ from Analog Devices, in a TSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DOUTA | output | Serial data output for ADC A, clocked out on the falling edge of SCLK, with 14 SCLK cycles required to read a 14-bit AD7367 result MSB first. |
| 2 | VDRIVE | power_in | Logic power supply input with a range of 2.7 V to 5.25 V that must never exceed DVCC or AVCC by more than 0.3 V, and must be at least 4.75 V to reach 1 MSPS for the AD7367. |
| 3 | DVCC | power_in | Digital supply voltage of 4.75 V to 5.25 V that should be shorted to AVCC and decoupled to DGND with 10 µF and 100 nF capacitors. |
| 4 | RANGE1 | input | Logic input for analog input range selection that sets the input range together with RANGE0 per Table 8. |
| 5 | RANGE0 | input | Logic input for analog input range selection that sets the input range together with RANGE1 per Table 8. |
| 6 | ADDR | input | Multiplexer select logic input that chooses Channel 1 or Channel 2 of both ADCs, latched on the rising edge of BUSY. |
| 7 | AGND | power_in | Analog ground reference for all analog circuitry, which must not be more than 0.3 V from DGND even on a transient basis. |
| 8 | AVCC | power_in | Analog supply for the ADC cores with a range of 4.75 V to 5.25 V, decoupled to AGND with 10 µF and 100 nF capacitors. |
| 9 | DCAPA | passive | Reference buffer decoupling pin for ADC A that takes a 680 nF capacitor and can be driven by an external 3 V reference when REFSEL is low. |
| 10 | VSS | power_in | Negative high-voltage analog supply that must be less than −11.5 V for all analog input ranges and be decoupled with 10 µF and 100 nF capacitors. |
| 11 | VA1 | input | Single-ended analog input channel 1 of ADC A whose range is set by RANGE0 and RANGE1. |
| 12 | VA2 | input | Single-ended analog input channel 2 of ADC A whose range is set by RANGE0 and RANGE1. |
| 13 | VB2 | input | Single-ended analog input channel 2 of ADC B whose range is set by RANGE0 and RANGE1. |
| 14 | VB1 | input | Single-ended analog input channel 1 of ADC B whose range is set by RANGE0 and RANGE1. |
| 15 | VDD | power_in | Positive high-voltage analog supply that must be greater than 11.5 V for all analog input ranges and be decoupled with 10 µF and 100 nF capacitors. |
| 16 | DCAPB | passive | Reference buffer decoupling pin for ADC B that takes a 680 nF capacitor and can accept an external 3 V reference when REFSEL is low. |
| 17 | AGND | power_in | Second analog ground pin that must connect to the system AGND plane and stay within 0.3 V of DGND. |
| 18 | REFSEL | input | Logic input that selects the on-chip 2.5 V reference when tied high or an external reference via DCAPA/DCAPB when tied to GND. |
| 19 | CS | input | Active-low chip select that frames the serial transfer and enables the DOUTA and DOUTB outputs when low. |
| 20 | SCLK | input | Serial clock logic input that clocks out conversion data from the device. |
| 21 | CNVST | input | Edge-triggered conversion start input whose falling edge starts a conversion and whose low level at end of conversion puts the part into power-down. |
| 22 | BUSY | output | Busy output that goes high when a conversion starts and stays high until the conversion completes. |
| 23 | DOUTB | output | Serial data output for ADC B, clocked out on the falling edge of SCLK, which also carries the second ADC result when CS is held low for a further 14 SCLK cycles. |
| 24 | DGND | power_in | Digital ground reference for all digital circuitry that must be within 0.3 V of AGND even on a transient basis. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | TSSOP-24 |
| Category | Data Converters |
| Pins | 24 |
## CAD (KiCad official)
- Symbol: `AD7367BRUZ`
- Footprint: `Package_SO:TSSOP-24_4.4x7.8mm_P0.65mm`
- 3D model: TSSOP-24 (KiCad packages3D, STEP)
- 3D model files: `ad7367bruz-etched.step` / `ad7367bruz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7367bruz.step` / `ad7367bruz.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Analog Devices datasheet](https://www.analog.com/media/en/technical-documentation/data-sheets/AD7366_7367.pdf) (28 pp, sha256 `73011d26fda7310e`, retrieved 2026-11-02, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ad7367bruz-datasheet.pdf)